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    IDELAY

    Abstract: XAPP701 xilinx mig user interface design A596 DS302 UG070 XAPP702 X701
    Text: Application Note: Virtex-4 Family R XAPP701 v2.0 March 12, 2007 DDR2 SDRAM Physical Layer Using Direct-Clocking Technique Author: Tze Yi Yeoh Summary This application note describes the DDR2 SDRAM physical layer design using the direct-clocking technique in a VirtexTM-4 device. The direct-clocking technique utilizes some of


    Original     		XAPP701 64-tap IDELAY XAPP701 xilinx mig user interface design A596 DS302 UG070 XAPP702 X701 PDF

    FIFO36

    Abstract: DWH-11 ISERDES ML561 mig ddr virtex XAPP853 iodelay CY7C1520JV18-300BZXC K7R643684M-FC30 DWL-11
    Text: Application Note: Virtex-5 Family R XAPP853 v1.2 October 6, 2008 Summary QDR II SRAM Interface for Virtex-5 Devices Author: Lakshmi Gopalakrishnan This application note describes the implementation and timing details of a Quad Data Rate (QDR II) SRAM interface for Virtex -5 devices. The synthesizable reference design leverages


    Original     		XAPP853 36-bit FIFO36 DWH-11 ISERDES ML561 mig ddr virtex XAPP853 iodelay CY7C1520JV18-300BZXC K7R643684M-FC30 DWL-11 PDF

    XC4VLX25-FF668

    Abstract: MT49H16M18FM-25 XAPP701 XC4VLX25 xilinx mig user interface design xc4vlx25ff668 X710 XAPP710 xilinx mig 020421
    Text: Application Note: Virtex-4 Family R XAPP710 v1.4 April 28, 2008 Synthesizable CIO DDR RLDRAM II Controller for Virtex-4 FPGAs Author: Benoit Payette Summary This application note describes how to use a Virtex -4 device to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. The reference design


    Original     		XAPP710 XC4VLX25-FF668 MT49H16M18FM-25 XAPP701 XC4VLX25 xilinx mig user interface design xc4vlx25ff668 X710 XAPP710 xilinx mig 020421 PDF

    NETARM

    Abstract: No abstract text available
    Text: NET+Works for NET+ARM Hardware Reference Guide TM This guide provides a description of the NET+ARM 15/40 hardware. Part Number/Version: 8833198D Release Date: September, 2000 NETsilicon, Inc. 411 Waverley Oaks Road Suite 227 Waltham, MA 02452 Tel: 781 647-1234 or (800) 243-2333


    Original     		8833198D NETARM PDF

    XC4VLX15-FF668

    Abstract: axi4 XC4VLX15-FF668-10 FIFO Generator User Guide XQR XQ artix7 ucf file XC6SLX150T-FGG484-2 LocalLink axi wrapper XILINX/fifo generator xilinx spartan
    Text: LogiCORE IP FIFO Generator v8.3 DS317 October 19, 2011 Product Specification Introduction The Xilinx LogiCORE IP FIFO Generator is a fully verified first-in first-out FIFO memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO


    Original     		DS317 XC4VLX15-FF668 axi4 XC4VLX15-FF668-10 FIFO Generator User Guide XQR XQ artix7 ucf file XC6SLX150T-FGG484-2 LocalLink axi wrapper XILINX/fifo generator xilinx spartan PDF

    mce 2500 microphone

    Abstract: PEUL70511-01 C807 009C MD10 MD11 MD14 ML7050LA 0934H C803C
    Text: PEUL70511-01 Preliminary ML70511 Family User’s Manual Bluetooth LSI Issue Date: September 2, 2002 Notation Classification Notation • Numeric value Description xxH xxb Represents a hexadecimal number Represents a binary number • Unit Word, W byte, B nibble, N


    Original     		PEUL70511-01 ML70511 mce 2500 microphone PEUL70511-01 C807 009C MD10 MD11 MD14 ML7050LA 0934H C803C PDF

    AK7738VQ

    Abstract: No abstract text available
    Text: [AK7738] AK7738 5ch ADC+4ch DAC+8ch SRC内蔵Multi DSP 1. 概 要 AK7738はマイクアンプ付きの24bitステレオADC, 入力セレクタ付きの24bitステレオADC24bitモノラ ルADC、4chの32bit DAC、サンプリング周波数192kHzまで対応の4系統ステレオSRC、DITに加え、


    Original     		AK7738] AK7738 AK7738ã 24bitã 32bit 192kHzã 2560step/fs 48kHzã AK7738VQ PDF

    MPC8641 and MPC8641D Integrated Host Processor

    Abstract: mpc8641drm MPC8641 eTSEC77 eTSEC GMII Initial rgmii specification 00FF CRC32 MPC8640 MPC8640D
    Text: Freescale Semiconductor Errata Document Number: MPC8641DCE Rev. 1, 07/2009 Chip Errata for the MPC8641 and MPC8641D This document details all known silicon errata for the MPC8641 and MPC8641D devices. Table 1 provides a revision history for this document.


    Original     		MPC8641DCE MPC8641 MPC8641D MPC8641D MPC8640 MPC8640D. MPC8641/D MPC8641 and MPC8641D Integrated Host Processor mpc8641drm eTSEC77 eTSEC GMII Initial rgmii specification 00FF CRC32 MPC8640D PDF

    FIFO36

    Abstract: K7R643684M-FC30 iodelay DWL-20 ML561 XAPP853 DWH-21 ISERDES BWH-01 Virtex-5 FPGA
    Text: Application Note: Virtex-5 Family R XAPP853 v1.3 June 7, 2010 Summary QDR II SRAM Interface for Virtex-5 Devices Author: Lakshmi Gopalakrishnan This application note describes the implementation and timing details of a Quad Data Rate (QDR II) SRAM interface for Virtex -5 devices. The synthesizable reference design leverages


    Original     		XAPP853 36-bit FIFO36 K7R643684M-FC30 iodelay DWL-20 ML561 XAPP853 DWH-21 ISERDES BWH-01 Virtex-5 FPGA PDF

    APA150

    Abstract: vhdl code for phy interface
    Text: AvnetCore: Datasheet Version 1.0, July 2006 POS-PHY Level 3 Link Intended Use: — Packet Processors — POS switches — PHY processors — UNI/MAC — POS bridges top_link Features: top_rx_link rd_data rd_stats empty a_empty rd_enb rd_clk wr_data wr_stats


    Original     		fifo16 af-phy-0143 32-bit 16-bit CH-2555 APA150 vhdl code for phy interface PDF

    Xilinx spartan xc3s400_ft256

    Abstract: XC3S400_FT256 XC3S400PQ208 XC3S250EPQ208 xc3s400TQ144 XC3S400FT256 xc3s1400afg676 XC3S700AFG484 XC3S500EPQ208 XC3S200FT256
    Text: Memory Interface Solutions User Guide UG086 v3.3 December 2, 2009 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,


    Original     		UG086 DQS10 DQS11 DQS12 DQS13 DQS14 DQS15 DQS16 DQS17 Xilinx spartan xc3s400_ft256 XC3S400_FT256 XC3S400PQ208 XC3S250EPQ208 xc3s400TQ144 XC3S400FT256 xc3s1400afg676 XC3S700AFG484 XC3S500EPQ208 XC3S200FT256 PDF

    Axcelerator FPGAs

    Abstract: No abstract text available
    Text: AvnetCore: Datasheet Version 1.0, July 2006 POS-PHY Level 3 Phy Intended Use: — Packet Processors — POS switches — PHY processors — UNI/MAC — POS bridges top_link Features: top_rx_link rd_data rd_stats empty a_empty rd_enb rd_clk wr_data wr_stats


    Original     		fifo16 af-phy-0143 32-bit 16-bit CH-2555 Axcelerator FPGAs PDF

    XAPP753

    Abstract: ISERDES OSERDES TMSC6000 RAMB16 TMS320C64xx cpu XC4VLX25 microblaze block architecture IPC-2141 NEWNES RADIO
    Text: Interfacing Xilinx FPGAs to TI DSP Platforms Using the EMIF Application Note XAPP753 v2.0.1 January 29, 2007 R R Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs. Except as stated herein,


    Original     		XAPP753 IPC-2141 IPC-D-317A, 0-13-084408-x) XAPP753 ISERDES OSERDES TMSC6000 RAMB16 TMS320C64xx cpu XC4VLX25 microblaze block architecture NEWNES RADIO PDF

    xilinx mig user interface design

    Abstract: OSERDES 128 MB DDR2 SDRAM ddr2 ram XAPP721 XAPP723
    Text: Application Note: Virtex-4 FPGAs R XAPP723 v1.4 October 17, 2007 DDR2 Controller (267 MHz and Above) Using Virtex-4 Devices Author: Karthi Palanisamy Summary DDR2 SDRAM devices offer new features that go beyond the DDR SDRAM specification and enable the DDR2 device to operate at data rates of 666 Mb/s. High data rates require higher


    Original     		XAPP723 64-Bit 72-nit xilinx mig user interface design OSERDES 128 MB DDR2 SDRAM ddr2 ram XAPP721 XAPP723 PDF

    AK7738VQ

    Abstract: No abstract text available
    Text: [AK7738] AK7738 Multi DSP with 5ch ADC + 4ch DAC + 8ch SRC 1. General Description The AK7738 is a highly integrated digital signal processor, including a 24-bit stereo ADC with MIC gain amplifiers, a 24-bit stereo ADC with input selector, a monaural ADC, two 32-bit stereo DACs, 4 stereo


    Original     		AK7738] AK7738 AK7738 24-bit 32-bit 192kHz, 2560step/fs 48kHz) AK7738VQ PDF

    Broadcom

    Abstract: BCM1125 BCM1250 BCM5821 BCM5841 BCM5841-1 BCM5841-2 BCM5841-3 BCM5841-4 Broadcom b
    Text: BCM5841 PRODUCT Brief BCM5841 MULTI-GIGABIT B C M 5 8 4 1 F E AT U R E S • World’s fastest IPsec security processor SECURITY S U M M A R Y PROCESSOR O F B E N E F I T S • Multiple BCM5841 performance versions offers customers tremendous flexibility • 4.8 Gbps IPsec acceleration


    Original     		BCM5841 BCM5841 BCM584x BCM5841-1: BCM5841-3: BCM5841-2: BCM5841-4: Broadcom BCM1125 BCM1250 BCM5821 BCM5841-1 BCM5841-2 BCM5841-3 BCM5841-4 Broadcom b PDF

    FIFO Generator User Guide

    Abstract: fifo generator xilinx datasheet spartan xilinx fifo generator 6.2 FIFO36 ecc88 Virtex xilinx logicore fifo generator 6.2 hamming vhdl vhdl code for asynchronous fifo UG070
    Text: FIFO Generator v4.2 DS317 October 10, 2007 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP FIFO Generator is a fully verified first-in first-out FIFO memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO


    Original     		DS317 FIFO Generator User Guide fifo generator xilinx datasheet spartan xilinx fifo generator 6.2 FIFO36 ecc88 Virtex xilinx logicore fifo generator 6.2 hamming vhdl vhdl code for asynchronous fifo UG070 PDF

    MPC8548ECE

    Abstract: SRIO-A004 Interrupt Vector Table MPC8548E e500v2 hard floating point rapid io mpc8548 sp-efs e500v2 rgmii specification MPC8548E eTSEC GMII Initial
    Text: MPC8548ECE Rev. 3, 10/2010 Freescale Semiconductor Chip Errata MPC8548E Chip Errata This document details all known silicon errata for MPC8548E PowerQUICC III devices. Table 1. Revision History Revision Date Substantive Changes 3 10/2010 • Added CPU-A001, CPU-A005, eTSEC 106, eTSEC 107, eTSEC-A001, eTSECA002, eTSEC-A004, PCI-Ex 42, PCIe-A001, SEC-A001, SRIO-A002, SRIO-A004,


    Original     		MPC8548ECE MPC8548E CPU-A001, CPU-A005, eTSEC-A001, eTSECA002, eTSEC-A004, PCIe-A001, SEC-A001, MPC8548ECE SRIO-A004 Interrupt Vector Table MPC8548E e500v2 hard floating point rapid io mpc8548 sp-efs e500v2 rgmii specification eTSEC GMII Initial PDF

    MPC8567E

    Abstract: pic 123 MPC8567 MPC8568 eTSEC79 edis E500V
    Text: MPC8568ECE Rev. 0, 12/2009 Freescale Semiconductor Chip Errata MPC8568E Chip Errata This document details all known silicon errata for MPC8568E and MPC8567E devices. Table 1. Document Revision History Revision Date 12/2009 Significant Changes Initial public release


    Original     		MPC8568ECE MPC8568E MPC8567E MPC8568E 0x8021 0x807D pic 123 MPC8567 MPC8568 eTSEC79 edis E500V PDF

    MPC8548ECE

    Abstract: MPC8548E AN3543 Jumbo GmbH 0x80310020 3M39E
    Text: Freescale Semiconductor Application Note Document Number: AN3543 Rev. 0, 07/2009 MPC8548E Version 2.1.x Changes Changes in Silicon from Version 2.0 to Version 2.1.x The MPC8548E Version 2.1.x silicon incorporates changes to fix known errata and address expanded capabilities.


    Original     		AN3543 MPC8548E MPC8548ECE) MPC8548ECE AN3543 Jumbo GmbH 0x80310020 3M39E PDF

    LSR5000

    Abstract: MSR-500 MSR500 LS29 MC-10118A FCR5000 72193 LCR5000 S19262J S19265J
    Text: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社


    Original     		S19262JJ3V0UM00 S19262JJ3V0UM MC-10118A EM1-D512 PD77630A 11non-FIFO C0901-A LSR5000 MSR-500 MSR500 LS29 FCR5000 72193 LCR5000 S19262J S19265J PDF

    XC7V2000TFLG1925

    Abstract: XC7V2000T-FLG1925-1 XC7K480T-FFG1156-1 XC6SLX150T-FGG900 Artix-7 FFG1156 xc5vlx XC6VLX760-FF1760-1 XILINX/fifo generator xilinx spartan
    Text: LogiCORE IP FIFO Generator v9.1 DS317 April 24, 2012 Product Specification Introduction The Xilinx LogiCORE IP FIFO Generator is a fully verified first-in first-out FIFO memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO


    Original     		DS317 XC7V2000TFLG1925 XC7V2000T-FLG1925-1 XC7K480T-FFG1156-1 XC6SLX150T-FGG900 Artix-7 FFG1156 xc5vlx XC6VLX760-FF1760-1 XILINX/fifo generator xilinx spartan PDF

    keypad matrix

    Abstract: relay KEC
    Text: FEATURES FUNCTIONAL BLOCK DIAGRAM 16-element FIFO for event recording 10 configurable I/Os allowing for such functions as Keypad decoding for a matrix of up to 5 x 5 Key press/release interrupts GPIO functions GPI with selectable interrupt level 100 kΩ or 300 kΩ pull-up resistors


    Original     		ADP5586 ADP5586 10-input/output 16-Ball 1-20-2011-A CB-16-10 keypad matrix relay KEC PDF

    08B4H

    Abstract: c803c CVSD pcm B800-0010H 09F0 09E8H 08B8H TU-S9 21EP4
    Text: PJUL70511-01 暫定 ML70511 ファミリ ユーザーズマニュアル Bluetooth LSI 発行日 2002 年 2 月 28 日 表記法 分類 表記法 説明 • 数値 xxH xxb 16 進数を表します。 2 進数を表します。 ■ 単位 ワード, WORD バイト, BYTE


    Original     		ML70511 PJUL70511-01 009CH ADSNM02 ADSNM01 ADSNM00 08B4H c803c CVSD pcm B800-0010H 09F0 09E8H 08B8H TU-S9 21EP4 PDF