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Catalog Datasheet	Type	Document Tags	PDF
iodelay Abstract: XAPP880 OSERDES pmbus verilog FIFO18E1 ML605 ISERDES example ml605 XAPP855 samtec QSE Text: Application Note: Virtex-6 FPGAs SFI-4.1 16-Channel SDR Interface with Bus Alignment Using Virtex-6 FPGAs XAPP880 v1.0 February 10, 2010 Author: Vasu Devunuri Summary This application note describes an SFI-4.1 reference design that implements the OIF-SFI4-01.01 interface [Ref 1], a 16-channel, source-synchronous LVDS interface operating	Original	16-Channel XAPP880 OIF-SFI4-01 16-channel, iodelay XAPP880 OSERDES pmbus verilog FIFO18E1 ML605 ISERDES example ml605 XAPP855 samtec QSE	PDF
XC7K325TFFG900-2 Abstract: XC7K325TFFG900 PC28F00AP30TF XC7K325T-ffg900 pc28f00ap30 adv7511 pcie microblaze RS232-UART pc28f00 DSP48E1s Text: 29 AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet DS669 v1.1 November 2, 2012 Product Specification Introduction The KC705 Embedded Kit MicroBlaze Processor Subsystem showcases various features of the KC705 evaluation board.	Original	KC705 DS669 XC7K325TFFG900-2 XC7K325TFFG900 PC28F00AP30TF XC7K325T-ffg900 pc28f00ap30 adv7511 pcie microblaze RS232-UART pc28f00 DSP48E1s	PDF
RAMB18E1 Abstract: FIFO36E1 FIFO18E1 RAMB36E1 RAMB36SDP FIFO18 RAMB18SDP RAMB36E1 read back Virtex-5 Ethernet development fifo vhdl Text: Virtex-6 FPGA Memory Resources User Guide UG363 v1.3.1 January 19, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	UG363 64-bit 72-bit RAMB18E1 FIFO36E1 FIFO18E1 RAMB36E1 RAMB36SDP FIFO18 RAMB18SDP RAMB36E1 read back Virtex-5 Ethernet development fifo vhdl	PDF
RAMB36E1 Abstract: RAMB18E1 Text: 7 Series FPGAs Memory Resources User Guide UG473 v1.9 October 2, 2013 The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL	Original	UG473 64-bit 72-bit RAMB36E1 RAMB18E1	PDF
RAMB36E1 Abstract: FIFO36 asynchronous fifo vhdl UG363 verilog code hamming vhdl code for 8 bit parity generator vhdl code for 9 bit parity generator vhdl code hamming DSP48E1 RAMB36 Text: Virtex-6 FPGA Memory Resources User [optional] Guide UG363 v1.0 June 24, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	UG363 64-bit 72-bit RAMB36E1 FIFO36 asynchronous fifo vhdl UG363 verilog code hamming vhdl code for 8 bit parity generator vhdl code for 9 bit parity generator vhdl code hamming DSP48E1 RAMB36	PDF
FIFO18E1 Abstract: UG363 FIFO36E1 RAMB36E1 RAMB18E1 ramb18 RAMB36SDP vhdl code for asynchronous fifo VIRTEX-6 UG363 RAMB36 Text: Virtex-6 FPGA Memory Resources User Guide UG363 v1.5 August 3, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	UG363 64-bit 72-bit FIFO18E1 UG363 FIFO36E1 RAMB36E1 RAMB18E1 ramb18 RAMB36SDP vhdl code for asynchronous fifo VIRTEX-6 UG363 RAMB36	PDF
XC7K325TFFG900 Abstract: XC7K325TFFG900-2 kintex7 XC7K325TFFG900 -2 Text: 28 AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet DS669 v2.0 April 23, 2013 Product Specification Introduction The KC705 Embedded Kit MicroBlaze Processor Subsystem showcases various features of the KC705 evaluation board.	Original	KC705 DS669 KC705 XC7K325TFFG900 XC7K325TFFG900-2 kintex7 XC7K325TFFG900 -2	PDF
RGMII constraints Abstract: axi ethernet lite software example XC7VX330T-FFG1761 ramb16bwer vhdl code for ethernet mac lite spartan 3 cisco 2821 SPARTAN-6 gtp 2011 0x000005fc XC7V585T-FFG1761 AXI4 lite verilog Text: LogiCORE IP AXI Ethernet v3.00a DS759 November 17, 2011 Product Specification Introduction LogiCORE IP Facts Table This document provides the design specification for the LogiCORE IP AXI Ethernet core. This core implements a tri-mode (10/100/1000 Mb/s) Ethernet	Original	DS759 1000BASE-X 32-bit RGMII constraints axi ethernet lite software example XC7VX330T-FFG1761 ramb16bwer vhdl code for ethernet mac lite spartan 3 cisco 2821 SPARTAN-6 gtp 2011 0x000005fc XC7V585T-FFG1761 AXI4 lite verilog	PDF