ECL 10131
Abstract: signetics 10131 10131dc 10131N 10131F 25CC C30C62
Text: S ignetics 10131 Flip-Flop Dual D-Type Master-Slave Flip-Flop Product Specification ECL Products DESCRIPTION The 10131 is a Dual Master-Slave Flip Flop. Each flip-flop can be clocked sepa rately by holding the common Clock in the LOW state and using the Clock
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10131N
10131F
1110mV
ECL 10131
signetics 10131
10131dc
10131N
10131F
25CC
C30C62
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ECL 100151
Abstract: 100151 PM710 100151F 100151Y
Text: Signetics 100151 Flip-Flop Hex D-Type Master-Slave Flip-Flop Product Specification ECL Products DESCRIPTION The 100151 contains six flip-flops with complement and data outputs, a master reset MR and a pair of common clock inputs. Data enter the flip-flop on the
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137mA
100151F
100151Y
740mVp-p
500ns
ECL 100151
100151
PM710
100151F
100151Y
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TS 4142
Abstract: No abstract text available
Text: cn !33National Semiconductor 54F/74F175 Quad D Flip-Flop General Description Features The ’F175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is
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33National
54F/74F175
15mum
TS 4142
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Untitled
Abstract: No abstract text available
Text: SCAN18374T SCAN18374T D Flip-Flop with TRI-STATE Outputs Literature Number: SNLS037 SCAN18374T D Flip-Flop with TRI-STATE Outputs General Description Features The SCAN18374T is a high speed, low-power D-type flip-flop featuring separate D-type inputs organized into dual
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SCAN18374T
SCAN18374T
SNLS037
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74107 pin diagram
Abstract: 74107 74LS107 74107 flip flop H/CI 74107 pin configuration 74LS107 1N3064 1N916 74LS LS107
Text: 74107, LS107 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION Th e '1 0 7 is a dual flip-flop with individual J, K, Clock and direct R eset inputs. The 7 4 1 0 7 Is a positive pulse-triggered flip flop. JK information is loaded into the
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74LS107
1N916,
1N3064,
500ns
74107 pin diagram
74107
74107 flip flop
H/CI 74107
pin configuration 74LS107
1N3064
1N916
74LS
LS107
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OBD II 2
Abstract: No abstract text available
Text: November 1994 Semiconductor & 54F/74F175 Quad D Flip-Flop General Description Features The ’F175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where do ck and clear inputs are common. The information on the p inputs is
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54F/74F175
74F175PC
20-3A
SS8-9998
SS-11)
OBD II 2
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74ACT374
Abstract: No abstract text available
Text: N ovem ber 1988 Revised January 1999 SEMICONDUCTOR TM 74AC374 • 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The AC /AC T374 is a high-speed, low -pow er octal D-type flip-flop featuring separate D-type inputs for each flip-flop
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74AC374
74ACT374
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LS534
Abstract: No abstract text available
Text: National Semiconductor DM74LS534 Octal D-Type Flip-Flop With TRI-STATE Outputs General Description The 'LS534 is a high speed, low power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI STATE outputs for bus oriented applications. A buffered
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DM74LS534
LS534
LS374
TL/F/9812-1
11111I
TL/F/9812-2
TL/F/9812-3
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Untitled
Abstract: No abstract text available
Text: MOTOROLA DUAL J-K FLIP-FLOP MC14027B The MC14Q27B dual J-K flip-flop has independent J, K, Clock {Q, Set S and Reset |R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions. CMOS SSI • • Diode Protection on A ll Inputs
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MC14Q27B
MC14027B
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Untitled
Abstract: No abstract text available
Text: 74LS377 Signetics Flip-Flop Octal D Flip-Flop With Clock Enable Product Specification Logic Products FEATURES • Ideal for addressable register applications • Clock Enable for address and data synchronization applications • Eight edge-triggered D flip-flops
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74LS377
20-pin
40MHz
SQL-20
500ns
500ns
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Untitled
Abstract: No abstract text available
Text: cn W e* National Semiconductor 54F/74F534 Octal D-Type Flip-Flop with TRI-STATE Outputs General Description Features The ’F534 is a high speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buff
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54F/74F534
74F534PC
54F534DM
74F534SC
74F534SJ
54F534FM
54F534LM
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T374M
Abstract: No abstract text available
Text: 74AC374 • 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The A C /AC T374 is a high-speed, low -pow er octal D-type flip-flop featuring separate D-type inputs fo r each flip-flop and 3-STATE outputs fo r bus-oriented applications. A buff
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74AC374
74ACT374
T374M
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Untitled
Abstract: No abstract text available
Text: 3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: - CMOS technology. The ALVCH162821 device can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flipflops are edge-triggered D-type flip-flops. On the positive
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20-BIT
250ps
MIL-STD-883,
200pF,
635mm
IDT74ALVCH162821
ALVCH162821:
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Untitled
Abstract: No abstract text available
Text: 3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: - CMOS technology. The ALVCH162821 device can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flipflops are edge-triggered D-type flip-flops. On the positive
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20-BIT
ALVCH162821
10-bit
20-bit
IDT74ALVCH162821
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74ls112 pin configuration
Abstract: 74ls112 function table 74LS112 74S112
Text: Signetics 74LS112, S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set So and Reset (R q) inputs, when LOW,
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74LS112,
1N916,
1N3064,
500ns
500ns
74ls112 pin configuration
74ls112 function table
74LS112
74S112
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PIN CONFIGURATION 7476
Abstract: pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output 74LS76 J-K Flip-Flop 7476
Text: 7476, LS76 Sjgnetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is positive pulse-trig gered. JK information is loaded into the
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74LS76
1N916,
1N3064,
500ns
500ns
PIN CONFIGURATION 7476
pin diagram of 7476
7476 PIN DIAGRAM
7476 FUNCTION TABLE
pin diagram of ttl 7476
7476 pin configuration
LS 7476
7476 PIN DIAGRAM input and output
J-K Flip-Flop 7476
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Untitled
Abstract: No abstract text available
Text: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 525ps propagation delay The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip-flop when the clock is LOW and is transferred to the slave and,
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SY10EL35
SY100EL35
525ps
SY10/100EL35
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Untitled
Abstract: No abstract text available
Text: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 525ps propagation delay The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip-flop when the clock is LOW and is transferred to the slave and,
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SY10EL35
SY100EL35
525ps
SY10/100EL35
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HEF4013BP
Abstract: hEF4013 HEF4013BT HEF4013BPN HEF4013BTD HEF4013BP data
Text: HEF4013B \ , flip-flops V _ DUAL D-TYPE FLIP-FLOP The HEF4013B is a dual D-type flip-flop which features independent set direct Sq , clear direct (Cq ), clock inputs (CP) and outputs (0 ,0 ). Data is accepted when CP is LOW and transferred to the output on
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HEF4013B
HEF4013B
HEF4013BP
hEF4013
HEF4013BT
HEF4013BPN
HEF4013BTD
HEF4013BP data
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PDF
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Untitled
Abstract: No abstract text available
Text: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 525ps propagation delay The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip-flop when the clock is LOW and is transferred to the slave and,
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SY10EL35
SY100EL35
525ps
SY10/100EL35
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Untitled
Abstract: No abstract text available
Text: INTEGRATED CIRCUITS 74F273A Octal D flip-flop Product specification 1996 Mar 12 IC15 Data Handbook Philips Semiconductors PHILIPS Philips Semiconductors Product specification Octal D flip-flop 74F273A All outputs will be forced Low independently of Clock or Data inputs
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74F273A
74F273A
74F377A
74F373
74F374
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JT40W
Abstract: CD4027B
Text: Z 537T CD4027B Types CMOS Dual J-K Master-Slave Flip-Flop High-Voltage Types {20-V o lt Rating The RCA-CD4027B is a single m onolithic chip integrated circuit containing tw o iden tical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provi
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CD4027B
RCA-CD4027B
RCA-CD4013B
13--Dynamic
JT40W
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PDF
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3rw 44
Abstract: 74ALS109A 74ALS109AD 74ALS109AN SM15C
Text: 7 4 A L S 109 A . FLIP-FLOP 74ALS109A Dual J-K>osltive Edge-Triggered Flip-Flops With Set and Reset Product Specification DESCRIPTION The 'ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, R, Clock, Set and Reset inputs; also true and complemen
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74ALS109A
ALS109A
74als
500ns
3rw 44
74ALS109AD
74ALS109AN
SM15C
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Untitled
Abstract: No abstract text available
Text: TOSHIBA T C74VH CT574AF/AFW/AFT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74VHCT574AF, TC74VHCT574AFW, TC74VHCT574AFT OCTAL D-TYPE FLIP-FLOP WITH 3 - STATE OUTPUT The TC74VHCT574A is an advanced high speed CMOS OCTAL FLIP-FLOP with 3 -STATE OUTPUT fabricated
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C74VH
CT574AF/AFW/AFT
TC74VHCT574AF,
TC74VHCT574AFW,
TC74VHCT574AFT
TC74VHCT574A
TEH72MÃ
TC74VHCT574AF/AFW/AFT
20PIN
200mil
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