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    FLOATING-POINT ARITHMETIC Search Results

    FLOATING-POINT ARITHMETIC Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TMPM4GQF15FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4GRF20FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP176-2020-0.40-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4KMFWAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4MMFWAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4NQF10FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation

    FLOATING-POINT ARITHMETIC Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    R3000A

    Abstract: functional diagram of ALU R3010A block alu IDT79R3081 R3081 2873 R3010A Integrated Device Technology CFC-1
    Text: R3010A Core RISC FLOATING POINT ACCELERATOR FPA CORE Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Hardware support of single- and double-precision operations: — Floating-Point Add — Floating-Point Subtract — Floating-Point Multiply


    Original     		PDF R3010A 50MHz R3000A 64-bit 32-bit R3010A functional diagram of ALU block alu IDT79R3081 R3081 2873 R3010A Integrated Device Technology CFC-1

    D-10

    Abstract: D-12 D-16 DSP96002 3F800000 DSP96002 APPLICATIONS DSP96002 fft
    Text: APPENDIX D D.1 FLOATING-POINT NUMBER STORAGE AND ARITHMETIC D.1.1 General The IEEE standard for binary floating point arithmetic provides for the compatibility of floating-point numbers across all implementations which use the standard by defining bit-level encoding of floating-point numbers.


    Original     		PDF 32-bit DSP96002 D-10 D-12 D-16 3F800000 DSP96002 APPLICATIONS DSP96002 fft

    C-15

    Abstract: C-16 DSP96002 DSP96002 fft
    Text: APPENDIX C IEEE ARITHMETIC C.1 FLOATING-POINT NUMBER STORAGE AND ARITHMETIC C.1.1 General The IEEE standard for binary floating point arithmetic provides for the compatibility of floating-point numbers across all implementations which use the standard by defining bit-level encoding of floating-point numbers.


    Original     		PDF 32-bit DSP96002 C-15 C-16 DSP96002 fft

    VHDL code for floating point addition

    Abstract: verilog code for floating point division ARITHMETIC COPROCESSOR processor control unit vhdl code vhdl code 8 bit processor 80C51 APEX20KC APEX20KE DP8051 verilog code for floating point multiplication
    Text: DFPAU Floating Point Arithmetic Coprocessor ver 2.05 OVERVIEW DFPAU is a Floating Point Arithmetic Coprocessor, designed to assist CPU in performing the floating point arithmetic computations. DFPAU directly replaces C software functions, by equivalent, very fast hardware


    Original     		PDF DP8051, 32-bit VHDL code for floating point addition verilog code for floating point division ARITHMETIC COPROCESSOR processor control unit vhdl code vhdl code 8 bit processor 80C51 APEX20KC APEX20KE DP8051 verilog code for floating point multiplication

    16 point bfp fft verilog code

    Abstract: verilog code for single precision floating point multiplication IFFT verilog code for FFT 16 point verilog code for floating point adder VERILOG code for FFT 1024 point how to test fft megacore verilog code for FFT 256 point verilog code radix 4 multiplication verilog code for 64 point fft
    Text: FFT/IFFT Block Floating Point Scaling Application Note 404 October 2005, ver. 1.0 Introduction The Altera FFT MegaCore® function uses block-floating-point BFP arithmetic internally to perform calculations. BFP architecture is a trade-off between fixed-point and full floating-point architecture.


    Original     		PDF

    DSP48 floating point

    Abstract: ieee floating point multiplier verilog DSP48 ieee floating point vhdl vhdl code of 32bit floating point adder vhdl code for floating point subtractor DS335 DSP48E vhdl code of floating point adder MULT18X18S
    Text: Floating-Point Operator v3.0 DS335 September 28, 2006 Product Specification Introduction The Xilinx Floating-Point core provides designers with the means to perform floating-point arithmetic on an FPGA. The core can be customized to allow optimization for operation, wordlength, latency, and interface.


    Original     		PDF DS335 IEEE-754 DSP48 DSP48E IEEE-754. DSP48 floating point ieee floating point multiplier verilog ieee floating point vhdl vhdl code of 32bit floating point adder vhdl code for floating point subtractor DSP48E vhdl code of floating point adder MULT18X18S

    fft algorithm

    Abstract: 8point fft matlab fft implementation on tms320c55x Block Floating Point Implementation SPRA948 cfft32 radix-2 TMS320C55X TMS320C5000 5.1 audio processor using matlab
    Text: Application Report SPRA948 − September 2003 A Block Floating Point Implementation for an N-Point FFT on the TMS320C55x DSP David Elam and Cesar Iovescu TMS320C5000 Software Applications ABSTRACT A block floating-point BFP implementation provides an innovative method of floating-point


    Original     		PDF SPRA948 TMS320C55x TMS320C5000 TMS320C55x fft algorithm 8point fft matlab fft implementation on tms320c55x Block Floating Point Implementation cfft32 radix-2 5.1 audio processor using matlab

    80960MC

    Abstract: C90FDAA2
    Text: Floating-Point Operation 7 CHAPTER 7 FLOATING-POINT OPERATION This chapter describes the floating-point processing capabilities of the 80960MC processor. The subjects discussed include the real number data types, the execution environment for floating-point operations, the floating-point instructions, and fault and exception handling.


    OCR Scan     		PDF 80960MC C90FDAA2

    80960SB

    Abstract: No abstract text available
    Text: Floating-Point Instructions 1Q CHAPTER 10 FLOATING-POINT INSTRUCTIONS This chapter describes the floating-point processing capabilities of the 80960SB processor. The subjects discussed include the real number data types, the execution environment for floating-point operations, the floating-point instructions, and fault and exception handling.


    OCR Scan     		PDF 80960SB

    i960TM

    Abstract: 400921FB
    Text: Floating-Point Operation 7 CHAPTER 7 FLOATING-POINT OPERATION This chapter describes the floating-point processing capabilities o f the i960 MC processor. The subjects discussed include the real number data types, the execution environment for floating-point operations, the floating-point instructions and fault and exception handling.


    OCR Scan     		PDF

    am29325

    Abstract: H-14 AM29325GC WF023740 ScansUX970 TB000640
    Text: Am29325 32-Bit Floating-Point Processor • Single VLSI device performs high-speed floating-point arithmetic - Floating-point addition, subtraction, and multiplication in a single clock cycle - Internal architecture supports sum-of-products, Newton-Raphson division


    OCR Scan     		PDF Am29325 32-Bit 32-bit, 16-bit WF023790 WF023800 WF023810 16-Bit, H-14 AM29325GC WF023740 ScansUX970 TB000640

    DSP-3201

    Abstract: No abstract text available
    Text: ANALOG DEVICES 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEATURES Complete Chipset Implementing Floating-Point Arithmetic Fully Compatible with IEEE Standard 754 Arithmetic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point


    OCR Scan     		PDF 32-Bit ADSP-3211 ADSP-3221 240ns 750mW 144-Lead OOUT31 DSP-3201

    Cy7C601

    Abstract: tyn 618 P5H2
    Text: PRODUCT DESCRIPTION CYPRESS ~ SEMICONDUCTOR CY7C608 RISC Floating-Point Controller Features • Provides interface between the CY7C601 Integer Unit and CY7C609 Floating-Point Unit • Provides SPARC compatible Floating-Point Arithmetic and registers • Very high performance


    OCR Scan     		PDF CY7C608 CY7C601 CY7C609 CY7C608-33GC CY7C608-25GC tyn 618 P5H2

    Untitled

    Abstract: No abstract text available
    Text: NOV 2 i « # 1 Am29C325 CMOS 32-Bit Floating-Point Processor > 3 DISTINCTIVE CHARACTERISTICS Single VLSI device performs high-speed single­ precision floating-point arithmetic Floating-point addition, subtraction, and multiplication in a single clock cycle


    OCR Scan     		PDF Am29C325 32-Bit 32-bit, 16-bit Am29325

    PD102

    Abstract: ncl 039 Am29C325 Am29325 AM29C33 pin diagram of amd am2 processor th02 H-14 AM27S43 Am29CPL14
    Text: A m 29C 325 CMOS 32-Bit Floating-Point Processor FINAL DISTINCTIVE CHARACTERISTICS • • Single VLSI device performs high-speed single­ precision floating-point arithmetic Floating-point addition, subtraction, and multiplication in a single clock cycle


    OCR Scan     		PDF Am29C325 32-Bit 32-bit, 16-bit Am29325 PD102 ncl 039 AM29C33 pin diagram of amd am2 processor th02 H-14 AM27S43 Am29CPL14

    Untitled

    Abstract: No abstract text available
    Text: in te l CHAPTER 7 FLOATING-POINT UNIT The Intel Architecture Floating-Point Unit FPU provides high-performance floating-point processing capabilities. It supports the real, integer, and BCD-integer data types and the floating­ point processing algorithms and exception handling architecture defined in the IEEE 754 and


    OCR Scan     		PDF 01fl070fl

    H-14

    Abstract: L-13 WF023740 ScansUX971 Am29C325
    Text: Am29C325 CMOS 32-Bit Floating-Point Processor ADVANCE INFORMATION DISTINCTIVE CHARACTERISTICS • • Single VLSI device performs high-speed floating-point arithmetic - Floating-point addition, subtraction, and multiplication in a single clock cycle - Internal architecture supports sum-of-products,


    OCR Scan     		PDF Am29C325 32-Bit 32-bit, 16-bit Am29325 WF023760 WF023790 WF023800 H-14 L-13 WF023740 ScansUX971

    Untitled

    Abstract: No abstract text available
    Text: 7 IEEE Floating-Point Conformance The 21164 supports the IEEE floating-point operations as defined by the Alpha architecture. Support for a complete implementation of the IEEE Standard fo r Binary Floating-Point Arithmetic ANSI/IEEE Standard 754 1985 is provided by a


    OCR Scan     		PDF

    29C325

    Abstract: No abstract text available
    Text: Am29C325 CMOS 32-B¡t Floating-Point Processor FINAL DISTINCTIVE CHARACTERISTICS • • Single VLSI device performs high-speed single­ precision floating-point arithmetic Floating-point addition, subtraction, and multiplication in a single clock cycle Internal architecture supports sum-of-products,


    OCR Scan     		PDF Am29C325 32-bit, 16-bit Am29325 29C325

    80387

    Abstract: WEITEK 3167 pinout 80387 programmers reference manual 50/weitek pcs
    Text: WTL 3167 FLOATING-POINT COPROCESSOR PRELIMINARY DATA June 1988 Features SINGLE-CHIP FLOATING-POINT COPROCESSOR IEEE FORM AT Designed for use with the Intel 80386 Conforms to the IEEE standard format for floating­ point arithmetic in both single- and double-precision


    OCR Scan     		PDF 121-pin 80387 WEITEK 3167 pinout 80387 programmers reference manual 50/weitek pcs

    weitek

    Abstract: ncl051 WTL1165-060-GC 80386 microprocessor pin out diagram floating point handling LT 5251 1N3062 68-PIN WTL1163 1164-060
    Text: WTL 1164/WTL 1165 64-BIT IEEE FLOATING POINT MULTIPLIER/ DIVIDER AND ALU PRELIMINARY DATA Features A COMPLETE FLOATING POINT ARITHMETIC SOLUTION FOR HIGH-SPEED PROCESSORS AND COPROCESSORS FULL 32-BIT AND 64-BIT FLOATING POINT FORMAT AN D OPERATIONS, CONFORMING TO


    OCR Scan     		PDF 1164/WTL 64-BIT 32-BIT weitek ncl051 WTL1165-060-GC 80386 microprocessor pin out diagram floating point handling LT 5251 1N3062 68-PIN WTL1163 1164-060

    ADSP-3201

    Abstract: ADSP3201
    Text: ANALOG DEVICES □ 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEA T U R ES Complete Chipset Implementing Floating-Point Arithmetic Fully Compatible with IEEE Standard 754 Arithmetic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point


    OCR Scan     		PDF 32-Bit ADSP-3201/ADSP-3202 ADSP-3211 ADSP-3221 240ns 750mW ADSP-3201 ADSP3201

    80387 programmers reference manual

    Abstract: weitek intel 80486 opcode sheet weitek 1167 82C301 intel 82C301 80386 programmers manual AJT20 WEITEK 3167 protected mode 80486
    Text: ABACUS 3167 FLOATING-POINT COPROCESSOR July 1990 1. Features SINGLE-CHIP FLOATING-POINT COPROCESSOR IEEE FORM AT Used with the Intel 80386 Conforms to the IEEE standard format for floating-point arithmetic in both single and double precision ANSI/IEEE Standard 754-1985


    OCR Scan     		PDF 121-pin 80387 programmers reference manual weitek intel 80486 opcode sheet weitek 1167 82C301 intel 82C301 80386 programmers manual AJT20 WEITEK 3167 protected mode 80486

    TMS34082

    Abstract: CID20 TMS34082A TMS34082B-40 MSA15-0 TMS34020 emulator
    Text: TMS34082A, TMS34082B GRAPHICS FLOATING-POINT PROCESSOR SCGS001A - D315Q, SEPTEMBER 1988 - REVISED SEPTEMBER 1992 • High-Performance Floating-Point RISC Processor Optimized for Graphics • TWo Operating Modes - Floating-Point Coprocessor for TMS34020 Graphics System Processor


    OCR Scan     		PDF TMS34082A, TMS34082B SCGS001A D315Q, TMS34020 TMS34082 TMS34082A-40, TMS34082B-40 CID20 TMS34082A MSA15-0 TMS34020 emulator