FPU COPROCESSOR Search Results

FPU COPROCESSOR Result Highlights (5)

Part	Manufacturer	Description
TMPM4GQF15FG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002
TMPM4GRF20FG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP176-2020-0.40-002
TMPM4KMFWAFG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003
TMPM4MMFWAFG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003
TMPM4NQF10FG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002

FPU COPROCESSOR Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
xf05C Abstract: 40490FDB FE93 F60002 fe89 Text: uM-FPU Floating Point Coprocessor V2 Datasheet Introduction The uM-FPU is a 32-bit floating point coprocessor that can be easily interfaced with microcontrollers to provide support for 32-bit IEEE 754 floating point operations and long integer operations. The uM-FPU is easy to	Original	32-bit 16-bit xf05C 40490FDB FE93 F60002 fe89	PDF
max232 in LED matrix display Abstract: MAX232 8250 uM-FPU v3.1 circuit diagram of MAX232 connection to pic e729 S1100 MAX232 PDIP-18 SOIC-18 max232 interface pic pc Text: uM-FPU V3.1 Datasheet 32-bit Floating Point Coprocessor Introduction The uM-FPU V3.1 chip easily interfaces to virtually any microcontroller using a SPI or I2C™ interface. Many microcontrollers used in embedded systems lack floating point support, but a wide range of sensors available today	Original	32-bit max232 in LED matrix display MAX232 8250 uM-FPU v3.1 circuit diagram of MAX232 connection to pic e729 S1100 MAX232 PDIP-18 SOIC-18 max232 interface pic pc	PDF
fpu coprocessor Abstract: 8087 coprocessor instruction set 8086 intel Programmers Reference Manual 8086 Programmers Reference Manual intel 286 interrupt & exception intel 8088 assembly language intel 286 Intel 487 SX Text: Guidelines for Writing FPU Exception Handlers 35 As described in “Floating-Point Unit”, the Intel Architecture supports two mechanisms for accessing exception handlers to handle unmasked FPU exceptions: native mode and MS-DOS compatibility mode. The primary purpose of this appendix is to provide detailed information to	Original		PDF
8088 assembly language manual Abstract: intel 8086 8086 assembly language reference manual Intel 8088 programmers reference exception processing sequence 8086 Programmers Reference Manual intel 8086 opcode sheet intel Programmers Reference Manual intel 286 pic 8086 data sheet Text: Guidelines for Writing FPU Exception Handlers 35 As described in “Floating-Point Unit”, the Intel Architecture supports two mechanisms for accessing exception handlers to handle unmasked FPU exceptions: native mode and MS-DOS compatibility mode. The primary purpose of this appendix is to provide detailed information to	Original		PDF
addressing modes 8086 Abstract: 8086 effective address calculation m94byte 8086 instruction set 8086 OPCODE DATA SHEET 8086 opcode sheet datasheet for 8086 up by intel roundup 8086 architecture notes 8086 opcode machine code Text: F FNOP — FYL2XP1 45 F (FNOP — FYL2XP1) 45.1 FNOP—No Operation Opcode Instruction Description D9 D0 FNOP No operation is performed. Description Performs no FPU operation. This instruction takes up space in the instruction stream but does not affect the FPU or machine context, except the EIP register.	Original	Virtual-8086 addressing modes 8086 8086 effective address calculation m94byte 8086 instruction set 8086 OPCODE DATA SHEET 8086 opcode sheet datasheet for 8086 up by intel roundup 8086 architecture notes 8086 opcode machine code	PDF
rk3188 Abstract: RK3188-T ARGB888 emmc boot sequence Text: RK3188Technical Reference ManualRev 1.2 Chapter 1 Introduction RK3188 is a low power, high performance processor for mobile phones, personal mobile internet device and other digital multimedia applications, and integrates quad-core Cortex-A9 with separately NEONand FPU coprocessor.	Original	RK3188Technical RK3188 1080p 60fps, 264/MVC/VP8 30fps, RK3188-T ARGB888 emmc boot sequence	PDF
MPC8247 Abstract: MPC8248 MPC8271 MPC8272 16k x 8 ram powerpc 603e advanced information 516-pin Text: Integrated Communications Processors MPC8272 PowerQUICC II Processor Family MPC8272 BLOCK DIAGRAM System Interface Unit SIU Memory Controllers GPCM/UPM/SDRAM Classic G2 MMUs 60x Bus Interface Unit FPU Power Management JTAG/COP Timers 60x Bus Bus Arbitration	Original	MPC8272 MPC8272 60x-to-PCI 32-bit MPC8247, MPC8248, MPC8271 10-Base-T, MPC8247 MPC8248 16k x 8 ram powerpc 603e advanced information 516-pin	PDF
ieee floating point alu in vhdl Abstract: ERC32 ieee floating point vhdl ieee floating point multiplier vhdl SPARC RT TSC691E TSC692E TSC693E RAM SEU ieee 32 bit floating point multiplier Text: SPARC Processor for SPACE Applications TEMIC Semiconductors is offering a SPARC RT Radiation Tolerant processor, based on SPARC V7 architecture, for space applications, consisting of three devices: integer unit (IU), the TSC691E, floating point unit (FPU), the TSC692E,	Original	TSC691E, TSC692E, TSC693E. ERC32, ieee floating point alu in vhdl ERC32 ieee floating point vhdl ieee floating point multiplier vhdl SPARC RT TSC691E TSC692E TSC693E RAM SEU ieee 32 bit floating point multiplier	PDF
TS68040 Abstract: microprocessor 5962-9314301MXA 5962-9314301MYC ATC 1184 296Bytes IF-FC2 CAPACITOR SMD 107C ts68030 TS68882 Text: TS68040 Third-Generation 32-bit Microprocessor Datasheet Features • • • • • • • • • • • • • • 26-42 MIPS Integer Performance 3.5-5.6 MFLOPS Floating-Point-Performance IEEE 754-Compatible FPU Independent Instruction and Data MMUs	Original	TS68040 32-bit 754-Compatible 32-bit, TS68000 0851B TS68040 microprocessor 5962-9314301MXA 5962-9314301MYC ATC 1184 296Bytes IF-FC2 CAPACITOR SMD 107C ts68030 TS68882	PDF
Untitled Abstract: No abstract text available Text: AT91SAM ARM-based Cortex-M4 Flash MCU SAM4E16E SAM4E8E PRELIMINARY DATASHEET Description The Atmel SAM4E series of Flash microcontrollers is based on the high-performance 32-bit ARM Cortex -M4 RISC processor and includes a floating point unit FPU . It	Original	AT91SAM SAM4E16E 32-bit	PDF
intel 8087 architecture Abstract: sahf instruction intel 8086 Arithmetic and Logic Unit -ALU 8087 coprocessor architecture 8086 instruction set 8086 opcode sheet free binary numbers multiplication 8088 instruction set intel 8086 opcode sheet procedure for converting to opcodes in 8086 Text: Floating-Point Unit 31 The Intel Architecture Floating-Point Unit FPU provides high-performance floating-point processing capabilities. It supports the real, integer, and BCD-integer data types and the floatingpoint processing algorithms and exception handling architecture defined in the IEEE 754 and 854	Original		PDF
DNA 1001 DL Abstract: intel 486 dx2 clock circuit 1708503 RSM AH-16 DPL-08 ST5X86 7830A TLB 3101 2N223 486DX Text: ST486 CORE Standard 486 Processor Core FEATURES • ■ ■ INDUSTRY STANDARD 486 COMPATIBILITY ON-CHIP FPU ON-CHIP 8KBYTE WRITE BACK L1 CACHE ■ ■ DX / DX2 MODE OF OPERATION ADVANCED POWER MANAGEMENT 1.1 DESCRIPTION The ST486 CPU is an advanced 486DX/DX2	Original	ST486 486DX/DX2 DNA 1001 DL intel 486 dx2 clock circuit 1708503 RSM AH-16 DPL-08 ST5X86 7830A TLB 3101 2N223 486DX	PDF
vhdl code 64 bit FPU Abstract: PPC440 fpu coprocessor power pc architecture Floating-Point Representation of Numbers APU FCM fpu fpga Text: Virtex-5 APU Floating-Point Unit v1.01a DS693 April 24, 2009 Product Specification Introduction LogiCORE IP Facts The Virtex-5 Auxiliary Processor Unit APU FloatingPoint Unit is an optimized FPU designed for the PowerPC 440 embedded microprocessor of the Virtex-5	Original	DS693 IEEE-754 vhdl code 64 bit FPU PPC440 fpu coprocessor power pc architecture Floating-Point Representation of Numbers APU FCM fpu fpga	PDF
renesas Abstract: STR 6456 str f 6456 str x 6456 STR 6454 str f 6454 REJ09B0051-0300 FR15 MOVI20S "vector instructions" saturation Text: REJ09B0051-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH-2A, SH2A-FPU Software Manual	Original	REJ09B0051-0300 32-Bit Unit2607 renesas STR 6456 str f 6456 str x 6456 STR 6454 str f 6454 REJ09B0051-0300 FR15 MOVI20S "vector instructions" saturation	PDF

ST 7 flus 56 Abstract: 7 flus 56 SMM 201 architecture of 80486DX2 block diagram of automatic flush system 486DX 486DX2 80486DX2 ST486DX ST486DX2 Text: ST486DX2V 66 and 80 MHz clock doubled 486 CPU PRELIMINARY DATA IMPROVED 486DX2 PERFORMANCE – Clock doubled core speeds up to 80 MHz – Integrated FPU 10% faster than 80486DX2 – Up to 40 MHz bus speeds for fast local bus systems INDUSTRY STANDARD 486 COMPATIBILITY	Original	ST486DX2V 486DX2 80486DX2 486DX 168-pin 208-pin ST486DX2V 486DX/DX2/DX4 ST 7 flus 56 7 flus 56 SMM 201 architecture of 80486DX2 block diagram of automatic flush system 80486DX2 ST486DX ST486DX2	PDF
Atmel 826 Abstract: TS88915T atmel 748 TS68882 Atmel 89c TIP 41c transistor TS68000 TS68040 TS6840 5962-9314301MXA Text: Features • • • • • • • • • • • • • • 26-42 MIPS Integer Performance 3.5-5.6 MFLOPS Floating-Point-Performance IEEE 754-Compatible FPU Independent Instruction and Data MMUs 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed	Original	754-Compatible 32-bit, TS68000 Atmel 826 TS88915T atmel 748 TS68882 Atmel 89c TIP 41c transistor TS68040 TS6840 5962-9314301MXA	PDF
tms390 Abstract: L64811 L64814 TMS390C sun sparc pinout Text: LSI LOGIC L64814 Floating-Point Unit FPU Preliminary Description The L64814 Floating-Point Unit (FPU) is a highperformance, CMOS implementation of the SPARC (Scalable Processor ARChitecture) FPU. The FPU combines a floating-point controller w ith a high-throughput floating-point processor	OCR Scan	L64814 tms390 L64811 TMS390C sun sparc pinout	PDF
MB86903 Abstract: instruction set Sun SPARC T3 CY7C601 Text: MB86903 ~ FUJITSU SPARC -BASED IU/FPU AUGUST 1991 DATA SHEET FE A T U R E S _ G E N E R A L D E S C R IP T IO N • Single chip im plementation o f SPARC IU and FPU based upon the SPARC architecture The MB86903 is the first commercially available pro	OCR Scan	MB86903 32-bit MB86903 instruction set Sun SPARC T3 CY7C601	PDF
Intergraph Abstract: Intergraph C300 C-421 Clipper C300 Clipper C400 C300 C311 C400 C411 C421 Text: IN T E R G R A P H C O R P / A D V A N C E D 42E D • M ö B a b S T D Q O G 2 ci2 b ■ I G P H . -T* 49-17- 32. 32-BIT C M O S CLIPPER Availability: Now for 40- and 50-MHz C300 chipsets, modules, and C311 CPU/FPU. Now for the C4 CPU and FPU chipset, at 40- and	OCR Scan	50-MHz 50-MHz. D0Q05T2 C411/C421. Intergraph Intergraph C300 C-421 Clipper C300 Clipper C400 C300 C311 C400 C411 C421	PDF
Untitled Abstract: No abstract text available Text: M B86934 FUJITSU MB8693X 32-BIT RISC EMBEDDED PROCESSOR September 2 1 ,1 9 9 4 PRELIMINARY INFORMATION FEATURES_ _ • 60 MHz operating frequency • SPARC» high performance RISC architecture • High Performance SPARC FPU, ANSI/IEEE 754	OCR Scan	B86934 MB8693X 32-BIT 411963fmgd SLDS-934-9401	PDF
tx486 Abstract: TI486 ti486dx2-80 A7 B14 CPGA168 486dx schematic i486dx2 K1534 TI486DX2-G80 486dx2 schematic Text: TI486DX2-G66, TI486DX2-G80 MICROPROCESSORS PC SYSTEMS PRODUCTS SRZS006A — MAY 1995 - 486DX Architecture and Performance -486-Compatible Instruction Set and Register Set —Integrated Floating-Point Unit FPU —Integrated 16-Bit Hardware Multiplier —On-Chip 8K-Byte, 32-Bit Instruction/Data	OCR Scan	TI486DX2-G66, TI486DX2-G80 SRZS006A 486DX -486-Compatible 16-Bit 32-Bit 486-Class 168-Pin 208-Pin tx486 TI486 ti486dx2-80 A7 B14 CPGA168 486dx schematic i486dx2 K1534 486dx2 schematic	PDF
W8701 Abstract: instruction set Sun SPARC T3 Cy7C601 weitek 8701 W8701-40 weitek instruction set Sun SPARC T5 w8720 a2054 Text: W8701 INTEGRATED SPARC-COMPATIBLE PROCESSOR FAMILY M arch 1992 Chapter 1. Technical Overview 1.1. Features SINGLE-CHIP SPARC-COMPATIBLE IU/FPU HIGH PERFORMANCE Combines SPARC-compatible integer and floating-point units on a single chip Highest-performance SPARC-compatible processor on	OCR Scan	W8701 207-pin 8701-025-GCD630 instruction set Sun SPARC T3 Cy7C601 weitek 8701 W8701-40 weitek instruction set Sun SPARC T5 w8720 a2054	PDF
OX520 Abstract: No abstract text available Text: I MB86934_ FUJITSU 930 Series 32-BIT RISC EMBEDDED PROCESSOR June 1996 FEATURES GENERAL DISCUSSION • 50 MHz operating frequency, 40 MHz operating fre quency when FIFO is used • SPARC* high performance RISC architecture • High Performance SPARC FPU, ANSI/IEEE 754	OCR Scan	MB86934_ 32-BIT 374T7SL DDlflb33 MB86934 0010b3M 256-PIN FPT-256C-C02 MB86934-25/50ZFVES OX520	PDF
instruction set Sun SPARC T3 Abstract: C602A TMS390C601 TMS390C60 tms390 TMS390C602A C601 fpu coprocessor Text: DÊC O9 um I TMS390C602A SPARC FLOATING-POINT UNIT _SPKS006—_D3669. JANUARY 1991 * Slngle-Chlp, SPARC'"-Compatible Floating-Point Unit FPU for the ’C601 Integer Unit (IU) • High-Performance — 25-ns Cycle Time — 4.2 Million Double-Precision Unpack	OCR Scan	25-ns 64-Blt TMS390C602A instruction set Sun SPARC T3 C602A TMS390C601 TMS390C60 tms390 TMS390C602A C601 fpu coprocessor	PDF

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FPU COPROCESSOR Search Results

FPU COPROCESSOR Result Highlights (5)

FPU COPROCESSOR Datasheets Context Search

xf05C

max232 in LED matrix display

fpu coprocessor

8088 assembly language manual

addressing modes 8086

rk3188

MPC8247

ieee floating point alu in vhdl

TS68040

Untitled

intel 8087 architecture

DNA 1001 DL

vhdl code 64 bit FPU

renesas

ST 7 flus 56

Atmel 826

tms390

MB86903

Intergraph

Untitled

tx486

W8701

OX520

instruction set Sun SPARC T3