Untitled
Abstract: No abstract text available
Text: GS8662T08/09/18/36E-333/300/250/200/167 72Mb SigmaDDR-II Burst of 2 SRAM • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write x36 and x18 and Nybble Write (x8) function
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Original
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GS8662T08/09/18/36E-333/300/250/200/167
165-Bump
144Mb
165-bump,
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PDF
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Untitled
Abstract: No abstract text available
Text: GS8662T07/10/19/37BD-450/400/350/333/300 72Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus
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Original
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GS8662T07/10/19/37BD-450/400/350/333/300
165-Bump
165-bump,
GS8662TxxBD-333T.
GS8662Txx
AN1021
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PDF
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Untitled
Abstract: No abstract text available
Text: GS8662T08/09/18/36E-333/300/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus • JEDEC-standard pinout and package
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Original
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GS8662T08/09/18/36E-333/300/250/200/167
165-Bump
144Mb
GS8662Txx
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PDF
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Untitled
Abstract: No abstract text available
Text: GS8662T19/37AE-400/375/333/300 72Mb SigmaCIO DDR-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
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Original
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GS8662T19/37AE-400/375/333/300
165-Bump
GS8662TxxAE-300T.
GS8662TxxAE
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PDF
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Untitled
Abstract: No abstract text available
Text: GS8662T08/09/18/36E-333/300/250/200/167 72Mb SigmaDDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
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Original
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GS8662T08/09/18/36E-333/300/250/200/167
165-Bump
144Mb
165-bump,
GS8662Txx
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package
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Original
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GS8662T08/09/18/36BD-400/350/333/300/250
165-Bump
165-bump,
72Mcumentation
AN1021
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PDF
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Untitled
Abstract: No abstract text available
Text: Preliminary GS8662T08/09/18/36E-333/300/267/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
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Original
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8662T08/09/18/36E-333/300/267/250/200/167
165-Bump
144Mb
165-bump,
packa/267/250/200/167
GS8662Txx
|
PDF
|
mhz300
Abstract: No abstract text available
Text: GS8662T07/10/19/37BD-450/400/350/333/300 72Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus
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Original
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GS8662T07/10/19/37BD-450/400/350/333/300
165-Bump
165-bump,
GS8662TxxBD-333T.
GS8662Txx
mhz300
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8662T07/10/19/37BD-450/400/350/333/300 72Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package
|
Original
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GS8662T07/10/19/37BD-450/400/350/333/300
165-Bump
GS8662TxxBD-333T.
GS8662Txx
AN1021
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
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Original
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GS8662T08/09/18/36E-333/300/267
165-Bump
165-bump,
GS866x36E-300T.
GS8662Txx
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8662T07/10/19/37BD-450/400/375/333 72Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–333 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface
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Original
|
GS8662T07/10/19/37BD-450/400/375/333
165-Bump
165-bump,
GS8662TxxBD-333T.
GS8662Txx
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
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Original
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GS8662T08/09/18/36BD-400/350/333/300/250
165-Bump
165-bump,
72M/250
AN1021
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8662T08/09/18/36E-250/200/167 72Mb SigmaDDR-II Burst of 2 SRAM • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write x36 and x18 and Nybble Write (x8) function
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Original
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GS8662T08/09/18/36E-250/200/167
165-Bump
144Mb
165-bump,
|
PDF
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AN1019
Abstract: No abstract text available
Text: AN1019 SigmaQuad-II+ and SigmaDDR-II+ On-Die Termination ODT Introduction When an electrical signal is transmitted along a transmission line, it is reflected back when it reaches the end of the line. That reflection induces noise which adversely affects the quality of the signal, thereby making it more difficult for the receiving device
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Original
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AN1019
AN1019
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PDF
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|
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Untitled
Abstract: No abstract text available
Text: Preliminary GS8662T08/09/18/36E-333/300/267/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
|
Original
|
8662T08/09/18/36E-333/300/267/250/200/167
165-Bump
144Mb
165-bump,
GS8662Txx
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8662T08/09/18/36BD-350M 165-Bump BGA Military Temp 72Mb SigmaDDR-IITM Burst of 2 SRAM Features • Military Temperature Range • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
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Original
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GS8662T08/09/18/36BD-350M
165-Bump
165-bump,
GS8662T36BD-300MT.
GS8662TxxB-350M
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8662T07/10/19/37BD-450/400/350/333/300 72Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package
|
Original
|
GS8662T07/10/19/37BD-450/400/350/333/300
165-Bump
GS8662TxxBD-333T.
GS8662Txx
AN1021
|
PDF
|
GS8662T18BD
Abstract: No abstract text available
Text: GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
|
Original
|
GS8662T08/09/18/36BD-400/350/333/300/250
165-Bump
165-bump,
pa662T08/09/18/36BD-400/350/333/300/250
AN1021
GS8662T18BD
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
|
Original
|
GS8662T08/09/18/36BD-400/350/333/300/250
165-Bump
165-bump,
AN1021
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8662T07/10/19/37BD-450/400/350/333/300 72Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface
|
Original
|
GS8662T07/10/19/37BD-450/400/350/333/300
165-Bump
GS8662TxxBD-333T.
GS8662Txx
|
PDF
|
GS8662T18BD-250
Abstract: GS8662T18BGD-250
Text: Preliminary GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus
|
Original
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GS8662T08/09/18/36BD-400/350/333/300/250
165-Bump
GS8662T18BD-250
GS8662T18BGD-250
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8662T08/09/18/36E-333/300/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus • JEDEC-standard pinout and package
|
Original
|
GS8662T08/09/18/36E-333/300/250/200/167
165-Bump
144Mb
GS8662Txx
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
|
Original
|
GS8662T08/09/18/36E-333/300/267
165-Bump
an866x36E-300T.
GS8662Txx
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8662T20/38AE-450/400/375/333/300 72Mb SigmaCIO DDR-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaCIO Interface
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Original
|
GS8662T20/38AE-450/400/375/333/300
165-Bump
144Mb
165-bump,
165-bum
GS8662TxxAE-300T.
GS8662TxxAE
|
PDF
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