ibm04181aulaa
Abstract: ibm sram
Text: Workstation cache applications up to 250MHz 1Mb High Performance SRAM Highlights Access Time 2.25 ns Pipeline , 5.7ns (Flow Thru), 6.0 ns (Register Latch) Cycle Time 4 ns (Pipeline ),4 ns (Flow Thru), 6 ns (Register Latch) Organizations 64K x 18, 32K x 36
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250MHz
250Mhz)
MO-163.
SA14-xxxx-00
07SA14xxxxrr*
ibm04181aulaa
ibm sram
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Untitled
Abstract: No abstract text available
Text: IBM04181AULAA IBM04361AULAA P relim inary 32K X 36 & 64K X 18 SR A M Features • 32K x 36 or 64K x 18 Organizations • 0.45 Micron CMOS Technology • Synchronous Register-Latch Mode Of Operation with Self-Timed Late Write • Single Differential PECL Clock compatible with
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IBM04181AULAA
IBM04361AULAA
4/17/Q7
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Untitled
Abstract: No abstract text available
Text: IBM04181AULAA IBM04361AULAA P relim inary 32K X 36 & 64K X 18 SRAM Features • 32K x 36 or 64K x 18 Organizations • 0.45 Micron CMOS Technology • Synchronous Register-Latch Mode Of Operation with Self-Timed Late Write • Single Differential PECL Clock compatible with
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IBM04181AULAA
IBM04361AULAA
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Untitled
Abstract: No abstract text available
Text: I = = — ='= Preliminary IBM04361AULAA IBM04181 AULAA 32K X 36 & 64K X 18 SRAM Features • 32K x 36 or 64K x 18 Organizations • 0.45 Micron CMOS Technology • Synchronous Register-Latch Mode Of Operation with Self-Timed Late Write • Single Differential PECL Clock compatible with
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IBM04361AULAA
IBM04181
GA14-4668-02
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ibm04181aulaa
Abstract: No abstract text available
Text: I =¥= = = = ’= P relim inary IBM04361AULAA IBM04181 AULAA 32K X 36 & 64K X 18 SR A M Features • 32K x 36 or 64K x 18 Organizations • 0.45 Micron CMOS Technology • Synchronous Register-Latch Mode Of Operation with Self-Timed Late Write • Single Differential PECL Clock compatible with
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IBM04361AULAA
IBM04181AULAA
H9967
GA14-4668-02
IBM04361
IBM04181
77H9967
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Untitled
Abstract: No abstract text available
Text: I = = — = -= P relim inary IBM04181AULAA IBM04361 AULAA 32K X 36 & 64K X 18 SR A M Features • 32K x 36 or 64K x 18 O rganizations • 0.45 M icron C M O S Technology • S ynchronous R egister-Latch M ode Of O peration w ith Self-Tim ed Late W rite
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IBM04181AULAA
IBM04361
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Untitled
Abstract: No abstract text available
Text: IBM04361BULAA IBM04181BULAA Preliminary 32K X 36 & 64K X 18 SRAM Features • 32K x 36 or 64K x 18 Organizations • 0.45 Micron CMOS Technology • Synchronous Register-Latch Mode Of Operation with Self-Timed Late Write • Single Differential PECL Clock compatible with
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IBM04361BULAA
IBM04181BULAA
GA15-5001-00
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