N1101
Abstract: c813c N11010
Text: PCI ExpressTM Clock Generator ICS841S02I DATA SHEET General Description Features The ICS841S02I is a PLL-based clock generator specifically designed for PCI_Express Clock Generation applications. This device generates a 100MHz HCSL clock. The device offers a HCSL
|
Original
|
PDF
|
ICS841S02I
ICS841S02I
100MHz
25MHz.
25MHz
N1101
c813c
N11010
|
5P49V5901
Abstract: No abstract text available
Text: PRELIMINARY DATASHEET IDT5P49V5901 PROGRAMMABLE CLOCK GENERATOR Description Features The IDT5P49V5901 is a programmable clock generator intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip
|
Original
|
PDF
|
IDT5P49V5901
IDT5P49V5901
5P49V5901
|
5P49V5901
Abstract: No abstract text available
Text: PRELIMINARY DATASHEET IDT5P49V5901 PROGRAMMABLE CLOCK GENERATOR Description Features The IDT5P49V5901 is a programmable clock generator intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip
|
Original
|
PDF
|
IDT5P49V5901
IDT5P49V5901
5P49V5901
|
IDTP9036A
Abstract: OM350
Text: 12V Wireless Power Transmitter IC for TX-A6 Product Datasheet IDTP9036A Features Description 5W Solution for Wireless Power Consortium WPC -Compliant Power Transmitter Design TX-A6 Conforms to WPC Specification Version 1.1 Specifications Reduced EMI To Meet Requirements of WPC
|
Original
|
PDF
|
IDTP9036A
IDTP9036A
OM350
|
WPC TX-A6
Abstract: NA6054-CE LG L29K-G2J1-24-Z Power Jack 300 inverter schematic OM350 thermistor R53 array resistor 10k 603 WT-1005660-12K2-A6-G block diagram of moving message display using 805 IDTP9020
Text: Single Chip 12V Wireless Power Transmitter IC for TX-A6 IDTP9036 Product Datasheet Features Description • Single-Chip 5W Solution for Wireless Power Consortium WPC -Compliant Power Transmitter Design TX-A6 • Conforms to WPC Specification Version 1.1 Specifications
|
Original
|
PDF
|
IDTP9036
WPC TX-A6
NA6054-CE
LG L29K-G2J1-24-Z
Power Jack 300 inverter schematic
OM350
thermistor R53
array resistor 10k 603
WT-1005660-12K2-A6-G
block diagram of moving message display using 805
IDTP9020
|
IDTP9030
Abstract: Y31-60014F TQFN-48 TH1 thermistor 4.7k ohm CAP SMD X7R 100NF 50V 10 HALF-bridge inverter om SMD CODE MARKING ldo 250v HPF 2a IDTP9020 schematic diagram 24V to 19V converter
Text: Single Chip Wireless Power Transmitter IC for TX-A1 Product Datasheet IDTP9030 Features Description • Single-Chip 5W Solution for Wireless Power Consortium WPC -compliant power transmitter design A1 • Conforms to WPC specification version 1.1 specifications
|
Original
|
PDF
|
IDTP9030
IDTP9030
110kHz
205kHz
Y31-60014F
TQFN-48
TH1 thermistor 4.7k ohm
CAP SMD X7R 100NF 50V 10
HALF-bridge inverter
om SMD CODE MARKING ldo
250v HPF 2a
IDTP9020
schematic diagram 24V to 19V converter
|
X1387
Abstract: No abstract text available
Text: Single Chip Wireless Power Transmitter IC for TX-A1 Product Datasheet IDTP9030 Features Description • Single-Chip 5W Solution for Wireless Power Consortium WPC -compliant power transmitter design A1 • Conforms to WPC specification version 1.1 specifications
|
Original
|
PDF
|
IDTP9030
X1387
|
dfn8 tray
Abstract: No abstract text available
Text: Single-Chip 5V Wireless Power Transmitter IC for TX-A5 and A11 Product Datasheet IDTP9035A Features Description 5W Solution for Wireless Power Consortium WPC -compliant power transmitter design A5/A11 Conforms to WPC specification version 1.1 specifications
|
Original
|
PDF
|
IDTP9035A
A5/A11
dfn8 tray
|
SEM 2006
Abstract: 7007S IDT CODE DATE TOP SIDE package marking FORMAT A12L A13L A14L IDT7007 IDT7007L IDT7007S MARKING A1L
Text: HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM IDT7007S/L Features ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 25/35/55ns max. – Industrial: 20/25/35/55ns (max.) – Commercial: 15/20/25/35/55ns (max.)
|
Original
|
PDF
|
IDT7007S/L
25/35/55ns
20/25/35/55ns
15/20/25/35/55ns
IDT7007S
850mW
IDT7007L
IDT7007
SEM 2006
7007S
IDT CODE DATE TOP SIDE package marking FORMAT
A12L
A13L
A14L
IDT7007L
IDT7007S
MARKING A1L
|
7007S
Abstract: A12L A13L A14L IDT7007 IDT7007L IDT7007S
Text: HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM IDT7007S/L Features ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 25/35/55ns max. – Industrial: 20/25/35/55ns (max.) – Commercial: 15/20/25/35/55ns (max.)
|
Original
|
PDF
|
IDT7007S/L
25/35/55ns
20/25/35/55ns
15/20/25/35/55ns
IDT7007S
850mW
IDT7007L
IDT7007
7007S
A12L
A13L
A14L
IDT7007L
IDT7007S
|
7007S
Abstract: No abstract text available
Text: HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM IDT7007S/L Features ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 25/35/55ns max. – Industrial: 20/25/35/55ns (max.) – Commercial: 15/20/25/35/55ns (max.)
|
Original
|
PDF
|
IDT7007S/L
25/35/55ns
20/25/35/55ns
15/20/25/35/55ns
IDT7007S
850mW
IDT7007L
IDT7007
7007S
|
7007S
Abstract: IDT7007 A12L A13L A14L IDT7007L IDT7007S IDT TOP SIDE package marking FORMAT
Text: HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM IDT7007S/L Features ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 25/35/55ns max. – Industrial: 20/25/35/55ns (max.) – Commercial: 15/20/25/35/55ns (max.)
|
Original
|
PDF
|
IDT7007S/L
25/35/55ns
20/25/35/55ns
15/20/25/35/55ns
IDT7007S
850mW
IDT7007L
IDT7007
7007S
A12L
A13L
A14L
IDT7007L
IDT7007S
IDT TOP SIDE package marking FORMAT
|
5901A
Abstract: 5P49V5901
Text: Programmable Clock Generator IDT5P49V5901 PRELIMINARY DATASHEET Description Features The IDT5P49V5901 is a programmable clock generator intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time
|
Original
|
PDF
|
IDT5P49V5901
IDT5P49V5901
5901A
5P49V5901
|
SiB4500BDY
Abstract: IDTP9035 OM350 PJ-018AH 6.3h 250v C2012X5R1E106M 60014f NQG48 WT-5050 32 pins tqfn 5x5 footprint
Text: Single-Chip 5V Wireless Power Transmitter IC for TX-A5 and A11 Product Datasheet IDTP9035 Features Description 5W Solution for Wireless Power Consortium WPC -compliant power transmitter design A5/A11 Conforms to WPC specification version 1.1 specifications
|
Original
|
PDF
|
IDTP9035
IDTP9035
A5/A11
110kHz
205kHz
SiB4500BDY
OM350
PJ-018AH
6.3h 250v
C2012X5R1E106M
60014f
NQG48
WT-5050
32 pins tqfn 5x5 footprint
|
|
Untitled
Abstract: No abstract text available
Text: DATASHEET ICS1894-44 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE Description Features The ICS1894-44 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC
|
Original
|
PDF
|
ICS1894-44
10BASE-T/100BASE-TX
ICS1894-44
10Base-T
100Base-TX
|
ICS1894
Abstract: ICS1894-32 IDT CODE DATE marking FORMAT ics
Text: DATASHEET ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Description Features The ICS1894-32 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC
|
Original
|
PDF
|
ICS1894-32
10BASE-T/100BASE-TX
ICS1894-32
10Base-T
100Base-TX
ICS1894
IDT CODE DATE marking FORMAT ics
|
ICS1894
Abstract: ICS1894-32 Tpll10
Text: DATASHEET ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Description Features The ICS1894-32 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC
|
Original
|
PDF
|
ICS1894-32
10BASE-T/100BASE-TX
ICS1894-32
10Base-T
100Base-TX
ICS1894
Tpll10
|
ICS1894-32
Abstract: ICS1894 1894K32L
Text: DATASHEET ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Description Features The ICS1894-32 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC
|
Original
|
PDF
|
ICS1894-32
10BASE-T/100BASE-TX
ICS1894-32
10Base-T
100Base-TX
ICS1894
1894K32L
|
1894K32L
Abstract: ICS1894 "Fast Link Pulse"
Text: DATASHEET ICS1894-32 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Description Features The ICS1894-32 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC
|
Original
|
PDF
|
10BASE-T/100BASE-TX
ICS1894-32
ICS1894-32
10Base-T
100Base-TX
100MHz.
1894K32L
ICS1894
"Fast Link Pulse"
|
Untitled
Abstract: No abstract text available
Text: DATASHEET I CS1 8 9 4 -3 2 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE Description Features The ICS1894-32 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision
|
Original
|
PDF
|
10BASE-T/100BASE-TX
ICS1894-32
10Base-T
100Base-TX
|
Untitled
Abstract: No abstract text available
Text: DATASHEET ICS1894-34 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE Description Features The ICS1894-34 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC
|
Original
|
PDF
|
10BASE-T/100BASE-TX
ICS1894-34
ICS1894-34
10Base-T
100Base-TX
100MHz.
|
a80502-75
Abstract: A80503 TT80503 Pentium SX969 BP80502 sl27s A80502 SL27J basic architecture of Pentium Processors intel m pentium 735
Text: Pentium Processor Specification Update Release Date: January 1999 Order Number 242480-041 The Pentium® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
|
Original
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: PRELIMINARY DATASHEET ICS1894-34 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE Description Features The ICS1894-34 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision
|
Original
|
PDF
|
ICS1894-34
10BASE-T/100BASE-TX
ICS1894-34
10Base-T
100Base-TX
|
Untitled
Abstract: No abstract text available
Text: HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial: 15/20/25/35/55ns max. – Industrial: 20/55ns (max.) – Military: 25/35/55ns (max.)
|
Original
|
PDF
|
15/20/25/35/55ns
20/55ns
25/35/55ns
IDT7008S
750mW
IDT7008L
IDT7008S/L
IDT7008
PN100-1,
|