Motorola AN-913
Abstract: 2791L M68000 MCF5102 9222L c2 sub
Text: SECTION 9 INSTRUCTION TIMINGS This section summarizes instruction timings for the MCF5102. Table 9-1 alphabetically lists instruction timings and their location in this section. Table 9-1. Instruction Timing Index Instruction Page Instruction Page Instruction
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MCF5102.
MCF5102
Motorola AN-913
2791L
M68000
9222L
c2 sub
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circuit in GPR
Abstract: 2W2C L18411
Text: S3CB018/FB018 8 INSTRUCTION SET INSTRUCTION SET OVERVIEW GLOSSARY This chapter describes the CalmRISC instruction set and the details of each instruction are listed in alphabetical order. The following notations are used for the description. Table 8-1. Instruction Notation Conventions
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S3CB018/FB018
8080h,
8043h]
00101100b
8080h]
807Eh]
8083h]
807Bh]
circuit in GPR
2W2C
L18411
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AHR0A
Abstract: 0088H s3fb018 Z/lnk+3056+pm
Text: S3CB018/FB018 8 INSTRUCTION SET INSTRUCTION SET GLOSSARY This chapter describes the CalmRISC instruction set and the details of each instruction are listed in alphabetical order. The following notations are used for the description. Table 8-1. Instruction Notation Conventions
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S3CB018/FB018
8080h,
8043h]
00101100b
8080h]
807Eh]
8083h]
807Bh]
AHR0A
0088H
s3fb018
Z/lnk+3056+pm
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bge 1,5
Abstract: diode m3 MARK S2 M11001
Text: Opcodes and Execution Times 1.1 1 Instruction Reference by Opcode This section lists the instruction encoding for each i960 Jx processor instruction. Instructions are grouped by instruction format and listed by opcode within each format. Table 1-1. Miscellaneous Instruction Encoding Bits
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80960Jx
bge 1,5
diode m3
MARK S2
M11001
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addressing modes in adsp-21xx
Abstract: addressing modes of adsp 21xx processors direct addressing mode in adsp-21xx ADSP-2100 digital signal processing using the ADSP-2100 processor shift register alu ADSP-2100 Family Assembler Tools
Text: Instruction Set Reference 15.1 15 QUICK LIST OF INSTRUCTIONS This chapter is a complete reference for the instruction set of the ADSP-2100 family. The instruction set is organized by instruction group and, within each group, by individual instruction. The list below shows all
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ADSP-2100
addressing modes in adsp-21xx
addressing modes of adsp 21xx processors
direct addressing mode in adsp-21xx
digital signal processing using the ADSP-2100
processor shift register alu
ADSP-2100 Family Assembler Tools
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diode m3
Abstract: diode M2 A 92 E-NAND MARK S2
Text: Opcodes and Execution Times B.1 B Instruction Reference by Opcode This section lists the instruction encoding for each i960 RM/RN I/O Processor instruction. Instructions are grouped by instruction format and listed by opcode within each format. Table B-1. Miscellaneous Instruction Encoding Bits
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FRB 914
Abstract: No abstract text available
Text: SECTION 9 INSTRUCTION SET This section describes individual instructions, including a description of instruction formats and notation and an alphabetical listing of RCPU instructions by mnemonic. 9.1 Instruction Formats Instructions are four bytes long and word-aligned, so when instruction addresses
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0x0000
0x0000
FRB 914
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R2S2
Abstract: ustat2 ADSP-210xx addressing mode CP10 dsp ADSP-210xx ADSP-21160 core i7 alu SF12 SF13 SF14
Text: 2 INSTRUCTION SUMMARY Figure 2-0. Table 2-0. Listing 2-0. Overview This instruction set summary provides a syntax summary for each instruction and includes a cross reference to each instruction’s reference page. The following summary topics appear in this chapter:
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ADSP-21160
2-14b.
R2S2
ustat2
ADSP-210xx addressing mode
CP10 dsp
ADSP-210xx
core i7 alu
SF12
SF13
SF14
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segment register
Abstract: 1001dl fcom 8d mod 16 counter 00sw ebx 36-10 CL1101 mod 4 counter st 3617
Text: Instruction Formats and Encodings 36 This chapter describes the instruction format for all Intel Architecture processors. 36.1 General Instruction Format All Intel Architecture instruction encodings are subsets of the general instruction format shown in Figure 36-1. Instructions consist of optional instruction prefixes in any order , one or two primary
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2431EA
Abstract: bcx 16 b2790 powerpc 476
Text: MPCxxx Instruction Set This chapter lists the MPCxxx instruction set in alphabetical order by mnemonic. Note that each entry includes the instruction formats and a quick reference ‘legend’ that provides such information as the level s of the PowerPC architecture in which the instruction may
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ebx 36-10
Abstract: CL1101 fcom 8d 1001dl 00sw st 3617 100-CR4
Text: Instruction Formats and Encodings 36 This chapter describes the instruction format for all Intel Architecture processors. 36.1 General Instruction Format All Intel Architecture instruction encodings are subsets of the general instruction format shown in Figure 36-1. Instructions consist of optional instruction prefixes in any order , one or two primary
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MPC823
Abstract: EWS300-24 instruction manual
Text: INSTRUCTION SET This section lists the MPC823 instruction set in alphabetical order by mnemonic. Each entry includes the instruction formats and a quick reference legend that provides information like the level s of the PowerPC architecture in which the instruction can be found, user- or
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MPC823
EWS300-24 instruction manual
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DST80
Abstract: 3521H
Text: <P.75Â7UGT U /CPWCN #FFTGUU 5RCEG =L/2* INSTRUCTION DESCRIPTION AND FORMATS The following section lists each instruction set, and describes the: Instruction Format Operation performed Flag Conditions Examples of the code The format for the instruction uses the following conventions:
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1110B
11110000B)
01111111B)
10001111B)
11110111B)
00000111B)
01101100B)
01101001B)
DST80
3521H
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PowerPC 601 instructions set
Abstract: 2021ME
Text: MPCxxx Instruction Set This chapter lists the MPCxxx instruction set in alphabetical order by mnemonic. Note that each entry includes the instruction formats and a quick reference ‘legend’ that provides such information as the level s of the PowerPC architecture in which the instruction may
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intel instruction set
Abstract: 80960CA 80960SA reference opword branch conditional unconditional instruction
Text: 1 Instruction Set Overview This chapter provides an overview of the i960 microprocessor family’s instruction set and i960 Jx processor-specific instruction set extensions. Also discussed are the assembly-language and instruction-encoding formats, various instruction groups and each group’s instructions.
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bge 1,5
Abstract: intel instruction set
Text: Instruction Set Overview 5 This chapter provides an overview of the i960 microprocessor family’s instruction set and i960 RM/RN I/O processor-specific instruction set extensions. Also discussed are the assembly-language and instruction-encoding formats, various instruction groups and each group’s
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powerpc 476
Abstract: No abstract text available
Text: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. MPCxxx Instruction Set This chapter lists the MPCxxx instruction set in alphabetical order by mnemonic. Note that each entry includes the instruction formats and a quick reference ‘legend’ that provides
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Untitled
Abstract: No abstract text available
Text: Instruction Set - Summary 4.0 Instruction Set 4.1 Instruction Set Summary A summary of the ARM710 instruction set is shown in Figure 7: Instruction Set Summary. Note: some instruction codes are not defined but do not cause the Undefined instruction trap to be taken,
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ARM710
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80960SA
Abstract: 80960SB 80960
Text: Instruction Set g CHAPTER 9 INSTRUCTION SET This chapter provides an overview of the instruction set for the 80960SA/SB processor. Included is a discussion of the instruction format, a summary of the instruction groups and the instructions in each group. This chapter gives detailed descriptions of each of the instructions. The instructions are listed
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80960SA/SB
80960SA
80960SB
80960
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qx25
Abstract: No abstract text available
Text: PIC16C9XX 15.0 INSTRUCTION SET SUMMARY Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 15-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 15-1
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PIC16C9XX
PIC16CXXX
14-bit
PIC16CXX
DS30444E
qx25
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microprocessor 80286 flag register
Abstract: addressing modes 80286 80286 microprocessor addressing modes GE 6066 B0286 Opcode list of 8086 microprocessor microprocessor 80288 8086 effective address calculation
Text: l n t e l 386 TM DX MICROPROCESSOR 6. INSTRUCTION SET This section describes the lntel3B6 DX instruction set. A table lists all instructions along with instruction encoding diagrams and clock counts. Further details of the instruction encoding are then provided in the
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Intel386
16-Bit
32-Bit
microprocessor 80286 flag register
addressing modes 80286
80286 microprocessor addressing modes
GE 6066
B0286
Opcode list of 8086 microprocessor
microprocessor 80288
8086 effective address calculation
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80960MC
Abstract: branch conditional unconditional instruction
Text: Instruction-Set Summary Q CHAPTER 6 INSTRUCTION-SET SUMMARY This chapter provides an overview of the instruction set for the 80960MC processor. Included is a discussion of the instruction format and a summary of the instruction groups and the instructions in each group.
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80960MC
branch conditional unconditional instruction
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branch conditional unconditional instruction
Abstract: i960 MC instruction
Text: Instruction Set Summary 6 CHAPTER 6 INSTRUCTION SET SUMMARY This chapter provides an overview o f the instruction set for the i960 MC processor. Included is a discussion o f the instruction format and a summary of the instruction groups and the instructions in each group.
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cmps a44
Abstract: No abstract text available
Text: 13 13.1 INSTRUCTION SET OVERVIEW The instruction set used by the Am186EM and Am188EM microcontrollers is identical to the 80C186/188 instruction set. An instruction can reference from zero to several operands. An operand can reside in a register, in the instruction itself, or in memory.
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Am186EM
Am188EM
80C186/188
Q257S25
cmps a44
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