IW4027B
Abstract: IW4027BD IW4027BN 08335 IZ40
Text: TECHNICAL DATA IW4027B Dual JK Flip-Flop The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positivegoing edge of the Clock. The active HIGH asynchronous Reset and
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IW4027B
IW4027B
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04215
Abstract: IW4027B IW4027BD IW4027BN
Text: TECHNICAL DATA IW4027B Dual JK Flip-Flop The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positivegoing edge of the Clock. The active HIGH asynchronous Reset and Set
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IW4027B
IW4027B
IW4027BN
Plasti03
IZ4027B
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IW4027BD
IW4027BN
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IL311ANM
Abstract: tda8362b ILa1519B1Q iff4n60 IN1307N tda8890 IL311AN IL91214AN MC74HC123AN IL258D
Text: SEMICONDUCTOR PRODUCTS SHORT FORM CATALOG INTEGRAL 2010-2011 INTEGRAL JSC reserves the right to make changes in device design, specifications and other information identified in this publication without notice and assumes no responsibility for the use of any device described herein.
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IW4027B
Abstract: IW4027BD IW4027BN
Text: TECHNICAL DATA IW4027B Dual JK Flip-Flop High-Voltage Silicon-Gate CMOS The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positivegoing edge of the Clock. The active HIGH asynchronous Reset and Set
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IW4027B
IW4027B
IW4027BD
IW4027BN
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