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    Amphion

    Abstract: vhdl code for 4 channel dma controller dct verilog code CS6650 ESVA vhdl code for transpose memory
    Text: CS6650 TM High Definition MPEG-2 Video Decoder Virtual Components for the Converging World The CS6650 high-definition MPEG2 decoder is designed to provide high performance solutions for a broad range of motion image applications. This highly integrated application specific core is developed for standard


    Original     		PDF CS6650 CS6650 DS6650-c Amphion vhdl code for 4 channel dma controller dct verilog code ESVA vhdl code for transpose memory

    CS6100

    Abstract: Huffman 1000X CS6150 Variable Length Decoder VLD
    Text: CS6150 Motion JPEG Decoder Virtual Components for the Converging World The CS6150 Motion JPEG M-JPEG Decoder is a highly integrated virtual component solution for leadingedge image decompression applications. Its high performance is capable of sustaining data rates of over 125


    Original     		PDF CS6150 CS6150 CS6100 DS6150-b Huffman 1000X Variable Length Decoder VLD

    CS31

    Abstract: CIRCUIT DIAGRAM 7404 functional DIAGRAM 7404 IESS-308 code 02HEX CS3110 CS3112 K3025 Artisan Components
    Text: CS3110/12 Reed-Solomon Encoders Virtual Components for the Converging World The CS3110 and CS3112 Reed-Solomon encoders are designed to provide high performance solutions for a broad range of applications requiring forward error correction. These application specific


    Original     		PDF CS3110/12 CS3110 CS3112 CS3110) CS3112) DS3110-b CS31 CIRCUIT DIAGRAM 7404 functional DIAGRAM 7404 IESS-308 code 02HEX K3025 Artisan Components

    CS3210

    Abstract: 02HEX CS3212 CSO3210
    Text: CS3210/12 Reed-Solomon Decoders Virtual Components for the Converging World The CS3210 and CS3212 Reed-Solomon decoders are designed to provide high performance solutions for a broad range of applications requiring forward error correction. These application specific virtual components


    Original     		PDF CS3210/12 CS3210 CS3212 CS3210) CS3212) 880Mbits DS3210-b 02HEX CSO3210

    CHN 530

    Abstract: chn 723 chn 448 CHN 727 CS4125 CS4130 chn 711 TSMC sram1 CS4100 CS4110
    Text: CS4100 ADPCM Speech Coders Virtual Components for the Converging World The CS4100 family of adaptive differential pulse code modulators ADPCMs is designed to provide high performance solutions for a broad range of applications requiring speech compression and decompression. These


    Original     		PDF CS4100 CS4100 DS4100-b CHN 530 chn 723 chn 448 CHN 727 CS4125 CS4130 chn 711 TSMC sram1 CS4110

    Convolutional Encoder

    Abstract: CS3530 Convolutional Block Interleaver time interleaver "Single-Port RAM" turbo encoder circuit
    Text: CS3530 TM Turbo Encoder Virtual Components for the Converging World The CS3530 Turbo Encoder is designed to provide efficient and high performance solutions for a broad range of applications requiring reliable communications in bandwidth scarce environments such as satellite and mobile


    Original     		PDF CS3530 CS3530 CDMA2000 DS3530 Convolutional Encoder Convolutional Block Interleaver time interleaver "Single-Port RAM" turbo encoder circuit

    CS3212

    Abstract: forney CS3210
    Text: CS3210/12 TM Reed-Solomon Decoders Virtual Components for the Converging World The CS3210 and CS3212 Reed-Solomon decoders are designed to provide high performance solutions for a broad range of applications requiring forward error correction. These application specific virtual components ASVCs


    Original     		PDF CS3210/12 CS3210 CS3212 CS3210) CS3212) 880Mbits CS3212 DS3210 forney

    system generator REED SOLOMON

    Abstract: 02HEX CS3214
    Text: CS3214 High Speed G.709/G,975 Compliant ReedSolomon Decoder - Preliminary Datasheet TM Virtual Components for the Converging World The CS3214 Reed-Solomon Decoder is designed to provide high performance solutions for forward error correction requirements and meets the ITU G.709 standard for Optical Transport Networks OTN providing


    Original     		PDF CS3214 709/G CS3214 DS3214 system generator REED SOLOMON 02HEX

    SHA-256 Cryptographic Accelerator

    Abstract: verilog code for 128 bit AES encryption CS5311 SHA-1 using vhdl SHA-256 verilog code for 8 bit AES encryption verilog code for aes encryption SHA-512 SHA256 verilog code for 32 bit AES encryption
    Text: CS5310/11/12 Standard Hash Algorithm SHA-1 & SHA-2 Cores TM Virtual Components for the Converging World The CS5310/11/12 Hashing Cores are designed to achieve data authentication in digital broadband, wireless, and multimedia systems. These high performance application specific silicon cores support the Secure Hash


    Original     		PDF CS5310/11/12 CS5310/11/12 CS5310 CS5311 SHA-256 DS5310 SHA-256 Cryptographic Accelerator verilog code for 128 bit AES encryption SHA-1 using vhdl verilog code for 8 bit AES encryption verilog code for aes encryption SHA-512 SHA256 verilog code for 32 bit AES encryption

    verilog code for 32 bit AES encryption

    Abstract: vhdl code for aes decryption vhdl code for AES algorithm verilog code for image encryption and decryption verilog code for 128 bit AES encryption vhdl code for aes vhdl code for aes image encryption and decryption vhdl code for aes 192 encryption block diagram simplex Voice encryption
    Text: CS5265/75 TM AES Simplex Encryption/Decryption Cores Virtual Components for the Converging World The CS5265 and CS5275 Simplex AES encryption/decryption1 cores are designed to achieve data privacy in digital broadband, wireless, and multimedia systems. These high performance application specific cores support


    Original     		PDF CS5265/75 CS5265 CS5275 DS5265/75 verilog code for 32 bit AES encryption vhdl code for aes decryption vhdl code for AES algorithm verilog code for image encryption and decryption verilog code for 128 bit AES encryption vhdl code for aes vhdl code for aes image encryption and decryption vhdl code for aes 192 encryption block diagram simplex Voice encryption

    vhdl code for AES algorithm

    Abstract: verilog code for 128 bit AES encryption vhdl code for aes vhdl code for aes decryption verilog code for image encryption and decryption CS524 CS4191 CS5200 CS5210-40 CS5250-80
    Text: CS5210-40 TM High Performance AES Encryption Cores Virtual Components for the Converging World The CS5210-40 series of encryption cores1 are designed to achieve data privacy and authenticity in digital broadband, wireless, and multimedia systems. These high performance application specific silicon cores support


    Original     		PDF CS5210-40 CS5210-40 CS5250-80 CS5200 DS5210/40 vhdl code for AES algorithm verilog code for 128 bit AES encryption vhdl code for aes vhdl code for aes decryption verilog code for image encryption and decryption CS524 CS4191

    adpcm

    Abstract: G716 CS4590
    Text: CS4590 TM High Channel Count ADPCM Speech Coder Preliminary Datasheet Virtual Components for the Converging World The CS4590 Adaptive Differential Pulse Code Modulator ADPCM core is designed to provide high performance solutions for a broad range of applications requiring high channel count speech compression and


    Original     		PDF CS4590 CS4590 DS4590 adpcm G716

    RS encoder

    Abstract: 02HEX CS3114 CS3114TM
    Text: CS3114 High Speed G.709/G.975 Compliant Reed-Solomon Encoder TM Virtual Components for the Converging World The CS3114 Reed-Solomon Encoder is designed to provide high performance solutions for forward error correction requirements and meets the ITU G.709 standard for Optical Transport Networks OTN providing


    Original     		PDF CS3114 709/G CS3114 DS3114 RS encoder 02HEX CS3114TM

    16-PSK

    Abstract: 16PSK viterbi decoder for tcm decoders branch metric XOR 7486 CS3410 64 tcm trellis differential encoder for psk Convolutional Encoder viterbi IESS-308/309
    Text: CS3410 TM High Speed Viterbi/TCM Decoder Virtual Components for the Converging World The CS3410 Viterbi/TCM Decoder is a high performance implementation suitable for a range of Forward Error Correction applications. This highly integrated Application Specific Virtual Component ASVC can be used in


    Original     		PDF CS3410 CS3410 De256 DS3410-a 16-PSK 16PSK viterbi decoder for tcm decoders branch metric XOR 7486 64 tcm trellis differential encoder for psk Convolutional Encoder viterbi IESS-308/309

    180NM

    Abstract: FPGA 456 CS3112 fpga implementation using rs(255,239) IESS-308 code CS3110 02HEX DS3110 N1 ASIC K3025
    Text: CS3110/12 TM Reed-Solomon Encoders Virtual Components for the Converging World The CS3110 and CS3112 Reed-Solomon encoders are designed to provide high performance solutions for a broad range of applications requiring forward error correction. These application specific cores are developed for high


    Original     		PDF CS3110/12 CS3110 CS3112 CS3110) CS3112) DS3110 180NM FPGA 456 fpga implementation using rs(255,239) IESS-308 code 02HEX N1 ASIC K3025

    CS2411

    Abstract: CS2411TK CS2411XV DS2411
    Text: CS2411 1024 Point Block Based FFT/IFFT Preliminary Datasheet TM Virtual Components for the Converging World The CS2411 is an online programmable, block-based architecture 1024-point FFT/IFFT core. It is based on a radix4 / radix-16 algorithm that performs FFT/IFFT computation in four computation passes. This highly integrated


    Original     		PDF CS2411 CS2411 1024-point radix-16 1024-word DS2411 CS2411TK CS2411XV

    idct vhdl code

    Abstract: iso 13818-2 transport stream huffman encoding and decoding audio signal using VHDL Amphion Semiconductor CS6651 fpga "motion detection" verilog for 8 point dct in xilinx vhdl code for demultiplexer huffman encoding and decoding using VHDL
    Text: CS6651 TM MPEG-2 Video Decoder for FPGA Virtual Components for the Converging World The CS6651 MPEG2 decoder is designed to provide high performance solutions for a broad range of motion image applications. This highly integrated application specific virtual component ASVC is for standard


    Original     		PDF CS6651 CS6651 DS6651 idct vhdl code iso 13818-2 transport stream huffman encoding and decoding audio signal using VHDL Amphion Semiconductor fpga "motion detection" verilog for 8 point dct in xilinx vhdl code for demultiplexer huffman encoding and decoding using VHDL

    vhdl code for huffman decoding

    Abstract: Motion JPEG Codec CS6190 jpeg encoder vhdl code huffman encoding and decoding using VHDL SS jpeg codec VHDL code DCT verilog code for huffman coding vhdl code for transpose memory verilog code for huffman encoding
    Text: CS6190 TM Motion JPEG Codec Virtual Components for the Converging World The CS6190 Motion JPEG M-JPEG Codec is a highly integrated virtual component solution for leading-edge image compression and decompression applications. Its high performance is capable of sustaining data rates of


    Original     		PDF CS6190 CS6190 DS6190 vhdl code for huffman decoding Motion JPEG Codec jpeg encoder vhdl code huffman encoding and decoding using VHDL SS jpeg codec VHDL code DCT verilog code for huffman coding vhdl code for transpose memory verilog code for huffman encoding

    CS6150

    Abstract: DS6150 "motion jpeg" jpeg decode decoder huffman CS6100 FPGA48
    Text: CS6150 TM Motion JPEG Decoder Virtual Components for the Converging World The CS6150 Motion JPEG M-JPEG Decoder is a highly integrated virtual component solution for leading-edge image decompression applications. Its high performance is capable of sustaining data rates of over 185 megasamples/sec – delivering full motion, full color video images up to 4 megapixels1. Fully compliant with the


    Original     		PDF CS6150 CS6150 CS6100 DS6150 "motion jpeg" jpeg decode decoder huffman FPGA48

    CS3411

    Abstract: Viterbi Decoder CS3410 viterbi IESS-308/309 CS3311 IESS-308 Convolutional Encoder details and application CSC3411AA base-10
    Text: CS3411 TM High Speed Viterbi Decoder Virtual Components for the Converging World The CS3411 Viterbi Decoder is a high performance implementation suitable for a range of Forward Error Correction applications. This highly integrated application specific core can be used in conjunction with other


    Original     		PDF CS3411 CS3411 CS3311 DS3411 Viterbi Decoder CS3410 viterbi IESS-308/309 CS3311 IESS-308 Convolutional Encoder details and application CSC3411AA base-10

    16 QAM modulation verilog code

    Abstract: 4 QAM modulator demodulator circuitry verilog code for lms adaptive equalizer cs3810 verilog code for TCM decoder VHDL Coding for Pulse Width Modulation vhdl coding for error correction and detection LMS adaptive filter model for FPGA vhdl CS-3810 CS3710
    Text: CS3810 TM 32 QAM Demodulator Virtual Components for the Converging World The CS3810 32 QAM broadband wireless demodulator core has been developed to provide an efficient and highly optimized solution for wireless data networks. Combined with the CS3710 32 QAM modulator core data


    Original     		PDF CS3810 CS3810 CS3710 155Mbps CS5200 DS3810 16 QAM modulation verilog code 4 QAM modulator demodulator circuitry verilog code for lms adaptive equalizer verilog code for TCM decoder VHDL Coding for Pulse Width Modulation vhdl coding for error correction and detection LMS adaptive filter model for FPGA vhdl CS-3810

    CS3214

    Abstract: 02HEX CS3214TK Reed Solomon decoder DS3214 system generator REED SOLOMON EXCESS 3 code generator and decoder
    Text: CS3214 High Speed G.709/G,975 Compliant ReedSolomon Decoder - Preliminary Datasheet TM Virtual Components for the Converging World The CS3214 Reed-Solomon Decoder is designed to provide high performance solutions for forward error correction requirements and meets the ITU G.709 standard for Optical Transport Networks OTN providing


    Original     		PDF CS3214 709/G CS3214 DS3214 02HEX CS3214TK Reed Solomon decoder system generator REED SOLOMON EXCESS 3 code generator and decoder

    radix-8 FFT

    Abstract: 2048-point IFFT radix-2 CS2420 CS2421 2048-POINT xilinx radix-2 fft xilinx
    Text: CS2421 TM 2048/8192-Point IFFT Preliminary Datasheet Virtual Components for the Converging World The CS2421 is an online programmable, 2048/8192-point Inverse Fast Fourier Transform IFFT core. This highly integrated application specific silicon core is based on the radix-4 algorithm and performs 2048-point or 8192point IFFT algorithms in three computation passes. The CS2421 IFFT core is available in both ASIC and FPGA


    Original     		PDF CS2421 2048/8192-Point CS2421 2048-point 8192point DS2421 radix-8 FFT IFFT radix-2 CS2420 2048-POINT xilinx radix-2 fft xilinx

    02HEX

    Abstract: CS3114
    Text: CS3114 High Speed G.709/G.975 Compliant Reed-Solomon Encoder TM Virtual Components for the Converging World The CS3114 Reed-Solomon Encoder is designed to provide high performance solutions for forward error correction requirements and meets the ITU G.709 standard for Optical Transport Networks OTN providing


    Original     		PDF CS3114 709/G CS3114 DS3114 02HEX