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    Samsung Semiconductor KM48S8030CT-GL

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    Bristol Electronics KM48S8030CT-GL 39
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    Samsung Semiconductor KM48S16030AFTH

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    Quest Components KM48S16030AFTH 28
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    Samsung Electro-Mechanics KM48S2020CT-G10

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    Bristol Electronics KM48S2020CT-G10 21 1
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    Samsung Semiconductor KM48S8030CT-G10

    IC,SDRAM,4X2MX8,CMOS,TSOP,54PIN,PLASTIC
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    Samsung Semiconductor KM48S8030BT-GH

    IC,SDRAM,4X2MX8,CMOS,TSOP,54PIN,PLASTIC
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    KM48S Datasheets (44)

    Part
    ECAD Model
    Manufacturer
    Description
    Curated
    Datasheet Type
    PDF
    KM48S16030 Samsung Electronics 4M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S16030A Samsung Electronics 128Mbit SDRAM 4M x 8-Bit x 4 Banks Synchronous DRAM LVTTL Original PDF
    KM48S16030AT-G/F10 Samsung Electronics 4M x 8-Bit x 4 banks synchronous DRAM. Max freq. 66 MHz(CL=2&3). Interface LVTTL Original PDF
    KM48S16030AT-G/F8 Samsung Electronics 4M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S16030AT-G/FA Samsung Electronics 4M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S16030AT-G/FH Samsung Electronics 4M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S16030AT-G/FL Samsung Electronics 4M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S16030B Samsung Electronics 128Mbit SDRAM 4M x 8-Bit x 4 Banks Synchronous DRAM LVTTL Original PDF
    KM48S16030BT-G/F10 Samsung Electronics 4M x 8-Bit x 4 banks synchronous DRAM LVTTL. Max freq. 66 MHz(CL=2&3). Original PDF
    KM48S16030BT-GF10 Samsung Electronics 4M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S16030BT-G/F8 Samsung Electronics 4M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S16030BT-G/FA Samsung Electronics 4M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S16030BT-G/FH Samsung Electronics 4M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S16030BT-G/FL Samsung Electronics 4M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S16030BT-GL Samsung Electronics KM48S16030BT 4MB x 8-Bit x 4Banks Synchronous DRAM Organization = 16Mx8 Bank/ Interface = 4B/LVTTL Refresh = 4K/64ms Speed = 75,80,1H,1L,10 Package = 54TSOP2 Power = C,l Production Status = Eol Comments = - Original PDF
    KM48S16030T-G/F10 Samsung Electronics 4M x 8-Bit x 4 banks synchronous DRAM LVTTL. Max freq. 100 MHz. Original PDF
    KM48S16030T-G/F8 Samsung Electronics 4M x 8-Bit x 4 banks synchronous DRAM LVTTL. Max freq. 125 MHz. Original PDF
    KM48S16030T-G/FH Samsung Electronics 4M x 8-Bit x 4 banks synchronous DRAM LVTTL. Max freq. 100 MHz. Original PDF
    KM48S16030T-G/FL Samsung Electronics 4M x 8-Bit x 4 banks synchronous DRAM LVTTL. Max freq. 100 MHz. Original PDF
    KM48S32230AT-F10 Samsung Electronics 8M x 8 Bit x 4 Banks Synchronous DRAM Scan PDF

    KM48S Datasheets Context Search

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    Type
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    PDF

    Untitled

    Abstract: No abstract text available
    Text: shrink-TSOP KM48S16030BN Preliminary CMOS SDRAM 128Mb SDRAM Shrink TSOP 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 July 1999 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 July 1999 shrink-TSOP


    Original     		KM48S16030BN 128Mb A10/AP PDF

    Untitled

    Abstract: No abstract text available
    Text: KM48S8020B CMOS SDRAM Revision History Revision .3 November 1997 - tRDL has changed 10ns to 12ns. - Binning -10 does not meet PC100 characteristics . So AC parameter/Characteristics have changed to 64M 2nd values. Revision .4 (February 1998) - Input leakage Currents (Inputs / DQ) are changed.


    Original     		KM48S8020B PC100 PDF

    Untitled

    Abstract: No abstract text available
    Text: Preliminary SDRAM R evision H istory R evision 1 M ay 1998 - ICC2 N va lu e (10m A) is cha ng ed to 12m A. Revision .2 (June 1998) - tSH (-10 binning) is revised. REV. 2 June '98 ELECTRONICS Preliminary


    OCR Scan     		KM48S8030C_ KM48S8030C KM48S8030C 10/AP PDF

    54PIN

    Abstract: KM48S16030
    Text: Preliminary CMOS SDRAM KM48S16030 4M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply The KM48S16030 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the


    Original     		KM48S16030 KM48S16030 A10/AP 54PIN PDF

    KM48S8030BT

    Abstract: No abstract text available
    Text: KM48S8030B CMOS SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The KM48S8030B is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG'S high performance CMOS technol­


    OCR Scan     		KM48S8030B KM48S8030B KM48S8030BT PDF

    5.6V

    Abstract: km-48 S8020
    Text: KM48S8020B CMOS SDRAM 4M x 8Bit x 2 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Dual banks operation • MRS cycle with address key programs CAS latency 2 & 3


    OCR Scan     		KM48S8020B KM48S8020B 10/AP 5.6V km-48 S8020 PDF

    KM48S8030BT

    Abstract: No abstract text available
    Text: KM48S8030B CMOS SDRAM Revision History Revision .3 November 1997 - tRDL has changed 10ns to 12ns. - Binning -10 does not meet PC100 characteristics . So AC parameter/Characteristics have changed to 64M 2nd values. Revision .4 (February 1998) - Input leakage Currents (Inputs / DQ) are changed.


    Original     		KM48S8030B PC100 KM48S8030BT PDF

    KM48S8030D

    Abstract: No abstract text available
    Text: KM48S8030D CMOS SDRAM 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 May 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 May 1999 KM48S8030D CMOS SDRAM Revision History Revision 0.0 May 15, 1999


    Original     		KM48S8030D 64Mbit A10/AP KM48S8030D PDF

    KM48S16030A

    Abstract: No abstract text available
    Text: KM48S16030A CMOS SDRAM 128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 June 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Jun. 1999 KM48S16030A CMOS SDRAM Revision History Revision 0.0 May 15, 1999


    Original     		KM48S16030A 128Mbit A10/AP KM48S16030A PDF

    KMM390S3320BT1-GA

    Abstract: 16MX8 32MX72 KMM390S1723BT1-GA samsung memory
    Text: SERIAL PRESENCE DETECT PC133 Registered DIMM PC133 Registered SDRAM DIMM 168pin Type SPD Specification REV. 0 Aug. 1999 REV. 0 Aug. 1999 SERIAL PRESENCE DETECT PC133 Registered DIMM KMM390S1723BT1-GA •Organization : 16MX72 •Composition : 16MX8 * 9ea •Used component part # : KM48S16030BT-GA


    Original     		PC133 168pin) KMM390S1723BT1-GA 16MX72 16MX8 KM48S16030BT-GA 4K/64ms 128bytes KMM390S3320BT1-GA 16MX8 32MX72 KMM390S1723BT1-GA samsung memory PDF

    48S160

    Abstract: 48S1603
    Text: Preliminary KM48S16030 CMOS SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address The KM48S16030 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits,


    OCR Scan     		KM48S16030 KM48S16030 48S160 48S1603 PDF

    Untitled

    Abstract: No abstract text available
    Text: KM48S8030B CMOS SDRAM Revision History Revision .3 N ovem ber 1997 - tRDL has changed 10ns to 12ns. - Binning -10 does not m eet PC100 characteristics . So AC param eter/C haracteristics have changed to 64M 2nd values. Revision .4 (February 1998) - Input leakage C urrents (Inputs / DQ) are changed.


    OCR Scan     		KM48S8030B PC100 10/AP PDF

    Untitled

    Abstract: No abstract text available
    Text: KM48S32230A CMOS SDRAM 256Mbit SDRAM 8M X 8bit X 4 Banks Synchronous DRAM LVTTL Revision 0.2 January 1999 Samsung Electronics reserves the right to change products or specification without notice. REV. 0.2 Jan. '99 KM48S32230A CMOS SDRAM R evision H isto ry


    OCR Scan     		KM48S32230A 256Mbit 10/AP PDF

    Untitled

    Abstract: No abstract text available
    Text: Preliminary CMOS SDRAM KM48S32230A 8M X 8Bit X 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply The KM48S32230A is 268,435,456 bits synchronous high data • LVTTL compatible with multiplexed address rate Dynamic RAM organized as 8 x 8,392,608 words by 8 bits,


    OCR Scan     		KM48S32230A KM48S32230A PDF

    KM48S8030AT

    Abstract: M14e
    Text: KM48S8030A CMOS SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION . • •• rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG'S high performance CMOS technol­ . . - JEDEC standard 3.3V power supply


    OCR Scan     		KM48S8030A KM48S8030A KM48S8030AT M14e PDF

    Untitled

    Abstract: No abstract text available
    Text: KM48S32230A CMOS SDRAM 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL Revision 0.4 JUN 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.4 JUN 1999 KM48S32230A CMOS SDRAM Revision History Revision 0.1 Jan. 05, 1999


    Original     		KM48S32230A 256Mbit A10/AP PDF

    Untitled

    Abstract: No abstract text available
    Text: KM48S8020B CMOS SDRAM Revision History Revision .3 November 1997 - tRDL has changed 10ns to 12ns. - Binning -10 does not meet PC100 characteristics . So AC param eter/Characteristics have changed to 64M 2nd values. Revision .4 (February 1998) - Input leakage Currents (Inputs / DQ) are changed.


    OCR Scan     		KM48S8020B PC100 PDF

    KM48S8020

    Abstract: a9333
    Text: KM48S8020A CMOS SDRAM 4M x 8Bit x 2 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION JEDEC standard 3.3V power supply •■ LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs - CAS Latency 2 & 3 Burst Length (1, 2, 4, 8 & full page)


    OCR Scan     		KM48S8020A KM48S8020A 7TL4142 KM48S8020 a9333 PDF

    Untitled

    Abstract: No abstract text available
    Text: Preliminary CMOS SDRAM KM48S32230A 8M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply The KM48S32230A is 268,435,456 bits synchronous high data • LVTTL compatible with multiplexed address rate Dynamic RAM organized as 8 x 8,392,608 words by 8 bits,


    OCR Scan     		KM48S32230A KM48S32230A 10/AP PDF

    16MX4

    Abstract: KMM390S823DT1-GA samsung note
    Text: SERIAL PRESENCE DETECT PC133 Registered DIMM Registered SDRAM PC133 DIMM 168pin SPD Specification REV. 1 July. 1999 REV. 1 July. '99 SERIAL PRESENCE DETECT PC133 Registered DIMM KMM390S823DT1-GA •Organization : 8MX72 •Composition : 8MX8 *9 •Used component part # : KM48S8030DT-GA


    Original     		PC133 168pin) KMM390S823DT1-GA 8MX72 KM48S8030DT-GA 4K/64ms 128bytes 256bytes 16MX4 KMM390S823DT1-GA samsung note PDF

    km48s2020ct

    Abstract: KM48S2020CT-G
    Text: KM48S2020C CMOS SDRAM Revision History Revision .4 November 1997 - t RDL has changed 10ns to 12ns. - Binning -10 does not meet PC100 characteristics . So AC parameter/Characteristics have changed to 16M 3rd values. Revision .5 (Feb. 1998) - Input leakage Currents (Inputs / DQ) are changed.


    Original     		KM48S2020C PC100 km48s2020ct KM48S2020CT-G PDF

    RA12

    Abstract: No abstract text available
    Text: Preliminary CMOS SDRAM KM48S32230A 8M X 8 Bit X 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • J E D E C s ta n d a rd 3 .3 V p o w e r s u p p ly T h e K M 4 8 S 3 2 2 3 0 A is 2 6 8 ,4 3 5 ,4 5 6 b its s y n c h ro n o u s high d a ta • L V T T L c o m p a tib le w ith m u ltip le x e d a d d re s s


    OCR Scan     		KM48S32230A A10/AP RA12 PDF

    54PIN

    Abstract: RA12
    Text: Preliminary CMOS SDRAM KM48S8020B Revision History Revision ,3 November 1997 •tRDL has changed 10ns to 12ns. •Binning -10 does not meet PC 100 characteristics . So AC parameter/Characteristics have changed to 64M 2nd values. 1 ELECTRONICS This Material Copyrighted By Its Respective Manufacturer


    OCR Scan     		KM48S8020B A10/AP 54PIN RA12 PDF

    Untitled

    Abstract: No abstract text available
    Text: KM48S16030B CMOS SDRAM 128Mbit SDRAM 4M X 8Bit X 4 Banks Synchronous DRAM LVTTL Revision 0.1 June 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Jun. 1999 ELECTRONICS KM48S16030B CMOS SDRAM R evision H istory


    OCR Scan     		KM48S16030B 128Mbit 10/AP PDF