32-PIN
Abstract: LH540202
Text: SHARp ^ blE ]> • i w ^ / m o m ô i a Q ? DG1D1MD 6Bb « S R P J /no p r e li m i n a r y I / U 4 - CMOS 5 1 2 x 9 / 1 0 2 4 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540201/02 is a FIFO First-ln, First-Out mem
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S1SD71S
D010140
CMOS512x9/1024x9
LH5496/97
Am/IDT/MS7201/02
28-Pin,
300-mil
600-mil
32-PIN
LH540202
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Untitled
Abstract: No abstract text available
Text: LH540201/02 PRELIMINARY CMOS 512 x 9 /1 0 2 4 x 9 A syn ch ro n o u s FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540201/02 is a FIFO First-In, First-Out mem ory device, based on fully-static CMOS dual-port SRAM
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LH540201/02
LH5496/97
Am/IDT/MS7201/02
28-Pin,
300-mil
600-mil
32-Pin
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Untitled
Abstract: No abstract text available
Text: PRODUCT PREVIEW LH540201 /02/03 FEATURES CMOS 512/1024/2048 x 9 Asynchronous FIFO FUNCTIONAL DESCRIPTION • Fast Access Times: 12/15/20/25/35 ns • Fast Fall-Through Time Internal Architecture Based on CM O S Dual-Port SRAM technology • Independently-Synchronized Operation of
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LH540201
28-Pin
32-Pin
LH5496/97/98
Am/IDT/MS7201
LH540201/02/03
S40301-I
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Untitled
Abstract: No abstract text available
Text: SHARP CORP S1E D 61607=10 0 0 0b5 3 ô 3 T7 «S R P J T - * ¿ - 3 5 ' LH540201/02 PRELIMINARY CMOS 512 x 9/1024 x 9 Asynchronous FIFO FUNCTIONAL DESCRIPTION FEATURES • Fast Access Times: 15/20/25/35/50/65/80 ns • Fast-Fall-Through Time Architecture Based on
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LH540201/02
000b53fl
LH5496/97
AnrVIDT/MS7201/02
28-Pin,
300-mil
600-mil
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Untitled
Abstract: No abstract text available
Text: LH540201A/02A FEATURES • Fast Accress Times: 10 ns Flag and Data • Fully Asynchronous Read and Write 5 1 2 x 9 , 1 K x 9 F IF O sion pins are provided, which allow these FIFOs to be expanded in depth without speed penalty. Retransmit capability is provided. Activating the retransmit pin resets
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LH540201A/02A
28-Pin,
300-mil
28-PIN
28QSOP
QSOP28-P-Q150)
Q28QSOP
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Untitled
Abstract: No abstract text available
Text: LH540201 02 PRELIMINARY CMOS 512 x 9/1024 x 9 Asynchronous FIFO FUNCTIONAL DESCRIPTION FEATURES • Fast Access Times: 15/20/25/35/50/65/80 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely
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PDF
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LH540201
LH5496/97
Am/IDT/MS7201/02
28-Pin,
300-mil
600-mil
32-Pin
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Untitled
Abstract: No abstract text available
Text: LH540201A/02A FEATURES • Fast Accress Times: 10 ns Flag and Data • Fully Asynchronous Read and Write sion pins are provided, which allow these FIFOs to be expanded in depth without speed penalty. Retransmit capability is provided. Activating the retransmit pin resets
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LH540201A/02A
28-PIN
28-Pin,
300-mil
LH540201A
LH540202A
Q28SQJ
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Untitled
Abstract: No abstract text available
Text: LH540206 FEATURES • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags
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LH540206
IDT7206
IDT7201
LH5496
LH540201
28-Pin,
300-mil
600-mil
LH540206
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Untitled
Abstract: No abstract text available
Text: LH540206 FEATURES • Fast Access Times: 20/25/35/50/65/80 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Rags
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LH540206
IDT7206
IDT7201
LH5496
LH540201
28-Pin,
300-mil
600-mil
LH54020ented
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Untitled
Abstract: No abstract text available
Text: LH540205 FEATURES • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Halt-Full, and Empty Status Rags
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LH540205
Am/IDT7205
IDT7201
LH5496
LH540201
28-Pin,
300-mil
600-mil
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Untitled
Abstract: No abstract text available
Text: LH540205 ADVANCE INFORMATION CMOS 8192 X 9 Asynchronous FIFO FEATURES operating in a depth-cascaded configuration, the Half-Full Flag is not available. • Fast Access Times: 20/25/35/50/65/80 ns Data words are read out from the LH540205’s output port in precisely the same order that they were written in
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LH540205
Am/IDT7205
IDT7201
LH5496
LH540201
28-Pin,
300-mil
600-mil
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IR2E27A
Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Text: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080
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Core28
IR2C24A/AN
IR2C26
IR2C30/N
IR2C32
IR2C33
IR2C34
IR2C36
IR2C38/N
IR2C43
IR2E27A
IR2C53
IR2E02
IR2E27
IR2E10
IR3N34
IR2E31A
IR2E01
IR2C07
ir2e31
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ak25
Abstract: 20U20
Text: MEMORIES FIFO Memories Caoaritv uapacny !Confi Jration «ordsxbits 64 x 8 0.5k 64 x 9 Model No. Supply current Operating Access time Cycle time fWjuancy (ns) MAX. (ns) MIN. Operating Standby (MHz) MAX. (mA) MAX. (mA) MAX. LH5481D/U-25 25 - 45 - LH5481D/U-35
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LH5481D/U-25
LH5481D/U-35
LH5491D/U-25
LH5491D/U-35
LH5496/D/U-20
LH5496/D/U-35
LHS496/D/U-50
LH540201AD/AN/AK/AU-10
LH590436M-20
LH59043-6M-25
ak25
20U20
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lh540206
Abstract: No abstract text available
Text: LH540206 FEATURES • Fast Access Times: 20/25/35/50/65/80 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Rags
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LH540206
IDT7206
IDT7201
LH5496
LH540201
28-Pin,
300-mil
600-mil
LH540206
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