LH5497 Search Results

QE RTB

Abstract: lh5497
Contextual Info: LH5497 FEATURES • • • • • • Fast Access Times: 15/20/25/35/50/65/80 ns PIN CONNECTIONS 28-PIN PDIP TOP VIEW w C Full C M O S Dual Port Memory Array Fully Asynchronous Read and Write Expandable in Width and Depth 1• 28 H v cc Dg C 2 27 □ d4

Contextual Info: LH5497/97H FEATURES • • Fast Access Times: 15 720/25/35/50/65/80 ns CMOS 1 K x 9 FIFO PIN CONNECTIONS 28-PIN PDIP TOP VIEW WC Full CMOS Dual Port Memory Array 1• 28 □ V CC DS C 2 27 □ d4 D a li 3 26 3 d5 • Fully Asynchronous Read and Write Dj C

IDT7202

Abstract: LH5497U-25 lh5497
Contextual Info: LH5497 FEATURES • • • Fast Access Times: 15/20/25/35/50/65/80 ns CMOS 1K x 9 FIFO PIN CONNECTIONS 28-PIN PDIP Full CMOS Dual Port Memory Array Fully Asynchronous Read and Write TOP VIEW 28 □ v cc WC 1 Dg d 2 27 □ d 4 D3 C 3 26 □ d 5 d2 4 25 □

organizational structure samsung

Abstract: CYPRESS SAMSUNG CROSS REFERENCE DALLAS cross reference VITELIC MK4501 ic cross reference book CY7C408 mosel KM75C02
Contextual Info: FIFO Cross Reference FIFO CROSS REFERENCE ORGANIZATIONAL STRUCTURE SHARP MODEL * COMPETITIVE VENDOR 256 X 36 X 2 LH5420 LH5481 64 X 8 64 X 9 LH5491 4,096 X 9 4,096 X 9 4,096 X 9 1,024 X 9 2,048 X 9 X LH5493 LH5494 LH5496/96H 512 X 9 4.096 LH5492 9 LH5497/97H

lh5497

Contextual Info: LH5497/ FEATURES • • • Fast Access Times: 15/20/25/35/50/65/80 ns 28-PIN PDIP TOP VIEW • Full, Half-Full, and Empty Status Flags • WC 1« 28 □ v cc D .C 2 27 □ D« 26 □ * R .C 3 Fully Asynchronous Read and Write Expandable in Width and Depth

are mx hf no

Contextual Info: LH5497 FEATURES • • Fast Access Times: 15/20/25/35/50/65/80 ns CMOS 1 K x 9 FIFO PIN CONNECTIONS 28-PIN PDIP TOP VIEW Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags

high level block diagram for asynchronous FIFO

Abstract: DIP28-W-300 LH540202 LJH540202
Contextual Info: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540202 is a FIFO First-In, First-Out memory device, based onfully-staticCMOSdual-portSRAM tech­ nology, capable of storing up to 1024 nine-bit words. It

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

toshiba 32k*8 sram

Abstract: M5M23C100 M5M5265 seeq DQ2816A M5M23C400 MB832001 HITACHI 64k DRAM TC511000 KM41C464 TC51464
Contextual Info: FUNCTION GUIDE MEMORY ICs 3. CROSS REFERENCE GUIDE 3.1 DRAM Density 64 K X 1 256K X 1 X4 1M X X 4M X X 3.2 Mode Org. 1 4 1 4 Samsung Toshiba Hitachi Fujitsu NEC MSM3764 KM4164 Page Okl F. Page KM41C256 TC51256 Nibble KM41C257 TC51257 HM51256 S. Column KM41C258

CMOS ASYNCHRONOUS FIFO 32 PIN

Abstract: LH540202 32-PIN
Contextual Info: LH540202 CMOS 1024 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540202 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 1024 nine-bit words. It

CM3P67202AL25

Abstract: AM7202A-35RC AM7205 IDT7201SA 67202 CMS1-67204 AM7205A-25RC AM7201-50RC DS2009R IDT7202SA50TP
Contextual Info: FIFO MATRA MHS FIFO Cross Reference AMD AMD Part-Number AM7201-25JC AM7201-25RC AM7201-35JC AM7201-35RC AM7201-50JC AM7201-50RC AM7202A-25JC AM7202A-25RC AM7202A-35JC AM7202A-35RC AM7202A-50JC AM7202A-50RC AM7203A-25JC AM7203A-25RC AM7203A-35JC AM7203A-35RC

Contextual Info: CMOS 1 K x 9 FIFO TO P V IEW 28-PIN PDIP • Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write w C 1« 28 Dg C 2 27 □ d3 3 26 □ d5 C o • Fast Access Times: 15 720/25/35/50/65/80 ns PIN CONNECTIONS LJ < o FEATURES d. o2 C 4 25 ZI De

41C1000

Abstract: fujitsu 814100 TC 55464 toshiba HN62304 hn623257 658128 816b 41c464 hn62324 M7202A
Contextual Info: MEM ORY ICs FUNCTION GUIDE 3. C R O S S REFERENCE GUIDE 3.1 DRAM Density Org. Samsung Mode Toshiba Hitachi Fujitsu H M 51 256 M B 81256 NEC Oki 64K X 1 Page K M 416 4 25 6 K X 1 F. Page KM 41C256 TC 51256 Nibble KM 41C257 TC51257 S. C olu m n KM 41C258 TC 51258

32PLCC

Contextual Info: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing

CMOS ASYNCHRONOUS FIFO 32 PIN

Abstract: 32-PIN LH540202
Contextual Info: LH540202 CMOS 1024 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540202 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 1024 nine-bit words. It

Contextual Info: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540202 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-portSRAMtechnology, capable of storing up to 1024 nine-bit words. It

Contextual Info: MEMORIES ★Under development • FIFO M emories Capacity Conlfeuralion word* x bits 64x8 0.5k 64 x 9 4.5k 512x9 1k x 9 9k 512 x 18 2k x 9 18k 1k x 18 256 x 36 x 2 4k x 9 36k 1k x 36 72k QFJ=PLCC 8k x 9 Modal No. LH5481D/U-25 LH5481D/U-35 LH5491D/U-25 LH5491D/U-35

stopwatch using 8051 microcontroller

Abstract: 3Gxxx S1249 32k sram card 20pin battery BA 92 SAMSUNG semiconductor replacement M46Z128Y-XXXPM1 245AB-XXX-IND 50K ohm Trimmer Trim Pot Variable Resistor DS0621-SDK si288
Contextual Info: SHORT tMWì DALLAS SEMICONDUCTOR APRIL 1996 http://www.dalsemi.com For the latest information about every product we make, visit our World Wide Web site. You’ll find the most complete, up-to-date information about our products available seven days a week, 24 hours a day. H ere’s just some o f what you’ll find:

AM7204

Abstract: IC Works cross DALLAS cross reference CY7C408
Contextual Info: FIFO Cross Reference FIFO CROSS REFERENCE ORGANIZATIONAL STRUCTURE COMPETITIVE VENDOR SHARP MODEL ' Cypress [ CY7C408 AMD i CY7C409 _ Cypress ACCESS TIME SHARP PACKAGE OPTIONS 35/25/15 MHz -h - Cypress LH5496/96H COMPETITIVE MODEL 35/25/15 MHz Am7201 DIP/PLCC

Contextual Info: MEMORIES FIFO M emories ★Under developm ent Type Capacity Configuration Operating frequency MHz MAX. Model No. 25 —i 35 Access time(ns) 15 20 25 35 Package SKDIP QFJ 28 28 28 28 28 28 32 — 28 28 32 28 32 28 32 28 32 50 DIP LH5481 LH5491 j — LH5496

AM7201-50RC

Abstract: MK4503-15N 7202A AM7203-35JC MK4503-65N MK4501 IDT7201L50P AM7202-25RC IDT7201S120P AM7203-50JC
Contextual Info: FIFO CROSS REFERENCE AMD MOSEL AM7200-25PC AM7200-35PC AM7200-50PC AM7200-65PC AM7200-80PC AM7200-25JC AM7200-35JC AM7200-50JC AM7200-65JC AM7200-80JC AM7200-25RC AM7200-35RC AM7200-50RC AM7200-65RC AM7200-80RC AM7201-25PC AM7201-35PC AM7201-50PC AM7201-65PC

Contextual Info: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540202 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM tech­ nology, capable of storing up to 1024 nine-bit words. It

Contextual Info: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing