Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    LPDDR 8GB Search Results

    LPDDR 8GB Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    AM3715CBPA Texas Instruments Sitara Processor: ARM Cortex-A8, 3D Graphics, LPDDR 515-POP-FCBGA -40 to 105 Visit Texas Instruments Buy
    AM3703CBCD100 Texas Instruments Sitara Processor: Arm Cortex-A8, LPDDR 515-POP-FCBGA -40 to 90 Visit Texas Instruments Buy
    AM1806EZWT3 Texas Instruments Sitara Processor: ARM9, LPDDR, DDR2, Display 361-NFBGA 0 to 90 Visit Texas Instruments Buy
    AM3715CBCD100 Texas Instruments Sitara Processor: Arm Cortex-A8, 3D Graphics, LPDDR 515-POP-FCBGA -40 to 90 Visit Texas Instruments Buy
    AM3715CUSA Texas Instruments Sitara Processor: Arm Cortex-A8, 3D Graphics, LPDDR 423-FCBGA -40 to 105 Visit Texas Instruments Buy

    LPDDR 8GB Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    MT29C4G48MAZBBAKQ-48 IT

    Abstract: MT29C8G96MAZBBDJV-48 IT MT29C4G96MAZBBCJG-48 mt29c4g96
    Text: Micron Confidential and Proprietary 168-Ball NAND Flash with LPDDR PoP Features NAND Flash and Mobile LPDDR 168-Ball Package-on-Package PoP Combination Memory (TI OMAP ) MT29C4G48MAZBBAKQ-48 IT: 4Gb x16 (NAND) with 2Gb x32 (LPDDR) MT29C4G96MAZBBCJG-48 IT: 4Gb x16 (NAND) with 4Gb x32 (LPDDR)


    Original     		PDF 168-Ball MT29C4G48MAZBBAKQ-48 MT29C4G96MAZBBCJG-48 MT29C8G96MAZBBDJV-48 09005aef855512a5 168ball MT29C4G48MAZBBAKQ-48 IT MT29C8G96MAZBBDJV-48 IT mt29c4g96

    MT29C4G48MAZAPAKQ-5

    Abstract: MT29C4G96MAZAPCJG-5 MT29C4G96M MT29C4G96MAZAPCJG-5IT MT29C4G48mazapakq MT29F8G16 lpddr2 mcp lpddr2 nand mcp MT29C8G96 samsung* lpddr2* pop package
    Text: Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP TI OMAP MCP Features NAND Flash and Mobile LPDDR 168-Ball Package-on-Package (PoP) MCP Combination Memory (TI OMAP ) MT29C4G48MAYAPAKQ-5 IT, MT29C4G48MAZAPAKQ-5 IT, MT29C4G48MAZAPAKQ-6 IT, MT29C4G96MAZAPCJG-5 IT,


    Original     		PDF 168-Ball MT29C4G48MAYAPAKQ-5 MT29C4G48MAZAPAKQ-5 MT29C4G48MAZAPAKQ-6 MT29C4G96MAZAPCJG-5 MT29C4G96MAZAPCJG-6 MT29C8G96MAZAPDJV-5 MT29C8G96MAZAPDJV-6 09005aef83ba4387 MT29C4G96M MT29C4G96MAZAPCJG-5IT MT29C4G48mazapakq MT29F8G16 lpddr2 mcp lpddr2 nand mcp MT29C8G96 samsung* lpddr2* pop package

    MT29F4G08ABA

    Abstract: MT29C4G48 ELPIDA LPDDR2 POP MT29C4G48MAZBAAKQ-5
    Text: Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP TI OMAP MCP Features NAND Flash and Mobile LPDDR 168-Ball Package-on-Package (PoP) MCP Combination Memory (TI OMAPŒ) MT29C4G48MAYBAAKQ-5 WT, MT29C4G48MAZBAAKQ-5 WT, MT29C4G96MAYBACJG-5 WT, MT29C4G96MAZBACJG-5 WT,


    Original     		PDF 168-Ball MT29C4G48MAYBAAKQ-5 MT29C4G48MAZBAAKQ-5 MT29C4G96MAYBACJG-5 MT29C4G96MAZBACJG-5 MT29C8G96MAYBADJV-5 MT29C8G96MAZBADJV-5 MT29F4G08ABA MT29C4G48 ELPIDA LPDDR2 POP

    MT29F4G08ABA

    Abstract: MT29F8G08A MT29F4G08ABAD MT29C4G96MAZ MT29F4G08ABB mt29f4g16aba MT29C4G96M MT29F4G08AB smd transistor marking BA1 MT29C8G96
    Text: Preliminary‡ Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP TI OMAP MCP Features NAND Flash and Mobile LPDDR 168-Ball Package-on-Package (PoP) MCP Combination Memory (TI OMAP ) MT29C4G48MAYAPAKQ-5 IT, MT29C4G48MAZAPAKQ-5 IT, MT29C4G48MAZAPAKQ-6 IT, MT29C4G96MAZAPCJG-5 IT,


    Original     		PDF 168-Ball MT29C4G48MAYAPAKQ-5 MT29C4G48MAZAPAKQ-5 MT29C4G48MAZAPAKQ-6 MT29C4G96MAZAPCJG-5 MT29C4G96MAZAPCJG-6 MT29C8G96MAZAPDJV-5 MT29C8G96MAZAPDJV-6 09005aef83ba4387 MT29F4G08ABA MT29F8G08A MT29F4G08ABAD MT29C4G96MAZ MT29F4G08ABB mt29f4g16aba MT29C4G96M MT29F4G08AB smd transistor marking BA1 MT29C8G96

    MT29F4G08ABA

    Abstract: MT29F4G08A MT29F8G08A MT29F4G08AB MT29F4G08ABAD MT29C MT29F16G08A Micron MT29F8G08
    Text: Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP TI OMAP MCP Features NAND Flash and Mobile LPDDR 168-Ball Package-on-Package (PoP) MCP Combination Memory (TI OMAP ) MT29C4G48MAYBAAKQ-5 WT, MT29C4G48MAZBAAKQ-5 WT, MT29C4G96MAYBACJG-5 WT, MT29C4G96MAZBACJG-5 WT,


    Original     		PDF 168-Ball MT29C4G48MAYBAAKQ-5 MT29C4G48MAZBAAKQ-5 MT29C4G96MAYBACJG-5 MT29C4G96MAZBACJG-5 MT29C8G96MAYBADJV-5 MT29C8G96MAZBADJV-5 MT29F4G08ABA MT29F4G08A MT29F8G08A MT29F4G08AB MT29F4G08ABAD MT29C MT29F16G08A Micron MT29F8G08

    Untitled

    Abstract: No abstract text available
    Text: BE230A Display Embedded System Features •TI 1GHz 32-bit ARM Cortex-A8 Single Core CPU •512MB LPDDR •eMMC 4.41 I/F 8GB •WINCE 6.0 CORE OS •Support SD/SDHC Card •7" TFT LCD with 800x480 Resulution •4-wired Resistive Touch Panel •1 x RS232C, 1xCAN BUS


    Original     		PDF BE230A 32-bit 512MB 800x480 RS232C, RS-232 LPDDR-400 512MB 191mm

    Untitled

    Abstract: No abstract text available
    Text: BE230C Display Embedded System Features IP66 for Front Bezel 512 •TI 1GHz 32-bit ARM Cortex-A8 Single Core CPU •512MB LPDDR •eMMC 4.41 I/F 8GB •WINCE 6.0 CORE OS •Support SD/SDHC Card •7" TFT LCD with 800x480 Resulution •4-wired Resistive Touch Panel


    Original     		PDF BE230C 32-bit 512MB 800x480 1xRS232C, RS-232 LPDDR-400 512MB RS232C

    NT6DM16M16AD-T1

    Abstract: 64M32 HP 3458 NT6DM16M16AD-T1I
    Text: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver Marking  VDD /VDDQ


    Original     		PDF 256Mb NT6DM16M16AD NT6DM8M32AC -16Meg 16M16 NT6DM16M16AD-T1 64M32 HP 3458 NT6DM16M16AD-T1I

    lpddr2 256mb

    Abstract: NT6DM8M32AC-T1 NT6DM16M16AD NT6DM8M32AC lpddr2 layout NT6DM8M32 Dual LPDDR2 lpddr2 256mb kgd lpddr2-s2
    Text: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver Marking  VDD /VDDQ


    Original     		PDF 256Mb NT6DM16M16AD NT6DM8M32AC -16Meg 16M16 lpddr2 256mb NT6DM8M32AC-T1 NT6DM8M32AC lpddr2 layout NT6DM8M32 Dual LPDDR2 lpddr2 256mb kgd lpddr2-s2

    NT6DM16M

    Abstract: No abstract text available
    Text: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver


    Original     		PDF 512Mb NT6DM32M16AD NT6DM16M32AC -32Meg 32M16 -16Meg 16M32 NT6DM16M

    NT6DM32M16AD-T1

    Abstract: NT6DM32M16AD NT6DM16M32AC-T1 NT6DM16M32AC NT6DM16M32AC-T3 216-ball NT6DM32M16AD-T3 256M16 lpddr2 256mb lpddr2 layout
    Text: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver


    Original     		PDF 512Mb NT6DM32M16AD NT6DM16M32AC -32Meg -16Meg -60-ball -90-ball NT6DM32M16AD-T1 NT6DM16M32AC-T1 NT6DM16M32AC NT6DM16M32AC-T3 216-ball NT6DM32M16AD-T3 256M16 lpddr2 256mb lpddr2 layout

    LPDDR 8Gb

    Abstract: lpddr2 256mb NT6DM32M16AD-T1 NT6DM32M16AD nanya lpddr2 spec
    Text: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver


    Original     		PDF 512Mb NT6DM32M16AD NT6DM16M32AC -32Meg -16Meg -60-ball -90-ball LPDDR 8Gb lpddr2 256mb NT6DM32M16AD-T1 nanya lpddr2 spec

    Untitled

    Abstract: No abstract text available
    Text: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver  Differential clock inputs (CK and /CK)


    Original     		PDF 256Mb NT6DM16M16AD NT6DM8M32AC -16Meg 16M16

    Epson EPD controller

    Abstract: eMMC "EPD controller" usb pen drive block diagram EPD controller S4J21210B ARm cortexA9 GPIO S4J21230B epd driving S4J21220B
    Text: S4J21010 High Resolution EPD Evaluation Platform • Overview The S4J21010 Evaluation Platform is used for the development of high resolution EPD solutions. It provides advanced display functions such as high speed page turning and smooth handwriting. This design package


    Original     		PDF S4J21010 S4J21010 300dpi) Epson EPD controller eMMC "EPD controller" usb pen drive block diagram EPD controller S4J21210B ARm cortexA9 GPIO S4J21230B epd driving S4J21220B

    Micron Technology

    Abstract: No abstract text available
    Text: Micron DRAM Products Overview August 2013 John Quigley – Micron FAE 2012 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and


    Original     		PDF 20Note/DRAM/TN4102 TN-41-04: TN-41-13: TN-46-02: TN-46-06: TN-46-11: TN-46-14: TN-47-19: TN-47-20: Micron Technology

    EDE2116ACBG

    Abstract: EDE2116ACBG-1J-F EDE1116AGBG-1J-F DDR3-800D ELPIDA lpddr DDR3-800E EDE1116AGBG EDJ1108DBSE DDR3 layout EDE1032AGBG
    Text: SELECTION GUIDE DRAM Selection Guide Document No. E1454E90 Ver.9.0 Date Published September 2009 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2009 DRAM Selection Guide CONTENTS 1. DDR3


    Original     		PDF E1454E90 240-pin M01E0706 EDE2116ACBG EDE2116ACBG-1J-F EDE1116AGBG-1J-F DDR3-800D ELPIDA lpddr DDR3-800E EDE1116AGBG EDJ1108DBSE DDR3 layout EDE1032AGBG

    movinand

    Abstract: samsung 32GB Nand flash MLC memory Samsung 8Gb MLC Nand flash Flex-OneNAND Samsung Samsung 16GB Nand flash oneDRAM OneNAND Samsung 32Gb Nand flash SAMSUNG moviNAND samsung 2GB Nand flash
    Text: Samsung Fusion Semiconductors Samsung Fusion Memory Software Flash DRAM The Next-Generation Technology for High-Performance Mobile Applications SRAM Logic What is Fusion Memory? As consumers continue their insatiable demand for higher-performance, ever-smaller


    Original     		PDF BR-07-MEM-001 movinand samsung 32GB Nand flash MLC memory Samsung 8Gb MLC Nand flash Flex-OneNAND Samsung Samsung 16GB Nand flash oneDRAM OneNAND Samsung 32Gb Nand flash SAMSUNG moviNAND samsung 2GB Nand flash

    A1930

    Abstract: No abstract text available
    Text: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle


    Original     		PDF 256Mb NT6SM8M32AK -16Meg 16M16 A1930

    NT6TL128M32AQ-G1

    Abstract: NT6TL256T32 NT6TL256T32AQ-G1 NT6TL128M32AQ-G0 NT6TL128M32 hynix lpddr2 NT6TL128T64AR-G0 NT6TL256 NT6TL128T64AR-G1I NT6TL256T32AQ-G2
    Text: 4Gb/8Gb LPDDR2-S4 SDRAM NT6TL128M32AI Q /NT6TL256T32AQ NT6TL256T32AS/NT6TL128T64AR(3/5) Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe (DQS, ) is transmitted/received with data, to be used in capturing data at the receiver


    Original     		PDF NT6TL128M32AI /NT6TL256T32AQ NT6TL256T32AS/NT6TL128T64AR NT6TL128M32AQ-G1 NT6TL256T32 NT6TL256T32AQ-G1 NT6TL128M32AQ-G0 NT6TL128M32 hynix lpddr2 NT6TL128T64AR-G0 NT6TL256 NT6TL128T64AR-G1I NT6TL256T32AQ-G2

    NT6TL256T32AQ

    Abstract: NT6TL128M32AI hynix lpddr2 NT6TL128M32AQ-G1 LPDDR2 1Gb Memory NT6TL128M32 Hynix 4Gb LPDDR2 NT6TL256T32AQ-G1 NT6TL128M32AQ-G0 Elpida LPDDR2 Memory
    Text: 4Gb/8Gb LPDDR2-S4 SDRAM NT6TL128M32AI Q /NT6TL256T32AQ NT6TL256T32AS/NT6TL128T64AR(3/5) Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe (DQS, ) is transmitted/received with data, to be used in capturing data at the receiver


    Original     		PDF NT6TL128M32AI /NT6TL256T32AQ NT6TL256T32AS/NT6TL128T64AR NT6TL256T32AQ hynix lpddr2 NT6TL128M32AQ-G1 LPDDR2 1Gb Memory NT6TL128M32 Hynix 4Gb LPDDR2 NT6TL256T32AQ-G1 NT6TL128M32AQ-G0 Elpida LPDDR2 Memory

    NT6SM32M16AG-S1

    Abstract: NT6SM16M32 128M32 NT6SM16M32AK NT6SM32M16AG Lpddr2 Idd1 8M32R NT6SM16M32AK-S1 lpddr2 layout lpddr2 256mb
    Text: 512Mb LPSDR SDRAM NT6SM32M16AG / NT6SM16M32AK / NT6SM16M32RAK Feature  Options Fully synchronous; all signals registered on positive edge of  Marking VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed


    Original     		PDF 512Mb NT6SM32M16AG NT6SM16M32AK NT6SM16M32RAK -32Meg -16Meg -54-ball -90-ball x13mm) 32M16 NT6SM32M16AG-S1 NT6SM16M32 128M32 Lpddr2 Idd1 8M32R NT6SM16M32AK-S1 lpddr2 layout lpddr2 256mb

    Lpddr2 Idd7

    Abstract: COMMAND42 lpddr2 256mb lpddr2 layout NT6SM32M16AG-S2 LPDDR2 1Gb Memory NT6SM16M32
    Text: 512Mb LPSDR SDRAM NT6SM32M16AG / NT6SM16M32AK / NT6SM16M32RAK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed


    Original     		PDF 512Mb NT6SM32M16AG NT6SM16M32AK NT6SM16M32RAK -32Meg -16Meg -54-ball -90-ball x13mm) 32M16 Lpddr2 Idd7 COMMAND42 lpddr2 256mb lpddr2 layout NT6SM32M16AG-S2 LPDDR2 1Gb Memory NT6SM16M32

    Lpddr2 Idd7

    Abstract: Jedec lpddr2 216-ball LPDDR 8Gb lpddr2-s2
    Text: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle


    Original     		PDF 256Mb NT6SM8M32AK -16Meg -54-ball -90-ball x13mm) 16M16 Lpddr2 Idd7 Jedec lpddr2 216-ball LPDDR 8Gb lpddr2-s2

    NT6SM16M16AG-S1

    Abstract: lpddr2-s2 NT6SM16M16AG NT6SM16M16AG-S1I 128T64
    Text: 256Mb LPSDR SDRAM NT6SM16M16AG NT6SM8M32AK Feature Options Fully synchronous; all signals registered on positive edge of z z Marking VDD /VDDQ system clock -1.8V/1.8V M Internal, pipelined operation; column address can be changed z z every clock cycle


    Original     		PDF 256Mb NT6SM16M16AG NT6SM8M32AK -16Meg -54-ball -90-ball x13mm) 16M16 NT6SM16M16AG-S1 lpddr2-s2 NT6SM16M16AG-S1I 128T64