SN74LV161

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

Contextual Info: LV161A, LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404C – APRIL 1998 – REVISED JULY 2003 D D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD LV161A . . . FK PACKAGE TOP VIEW A B NC

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

7054F

Abstract: BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557
Contextual Info: INDEX General General Information Semiconductor Packages Sales Locations Microcontroller Microcontroller General MultiChipModules Smart Card Micro. Overview Micro. Shortform Micro. Hardware Manual Micro. Program. Manual Micro. Application Notes LCD Controller / Driver

SN74 schmitt trigger

Abstract: SDYU001 SN54LV00A SN54LV02A SN54LV04A SN54LV05A SN54LV08A SN54LV14A SN54LV32A SN54LV74A
Contextual Info: LVC and LV LowĆVoltage CMOS Logic Data Book 1998 Logic Products General Information LVC Gates and MSI LVC Octals LVC Widebus LVC 3.3-V to 5-V Translators and Cable Drivers LV Gates and MSI LV Octals Application Reports Mechanical Data LVC and LV Low-Voltage CMOS Logic

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

SN74LV161

Abstract: A115-A C101 SN54LV161A SN74LV161A
Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404D − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404E − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4 13

dallas 8820

Contextual Info: LV161A, LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404B – APRIL 1998 – REVISED DECEMBER 2000 D D D D D D D D description LV161A . . . J OR W PACKAGE LV161A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW CLR CLK A B C D ENP GND 1 16 2

A115-A

Abstract: C101 SN54LV161A SN74LV161A
Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

A115-A

Abstract: C101 SN54LV161A SN74LV161A
Contextual Info: LV161A, LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404B – APRIL 1998 – REVISED DECEMBER 2000 D D D D D D D D description LV161A . . . J OR W PACKAGE LV161A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW CLR CLK A B C D ENP GND 1 16 2

Contextual Info: LV161A, LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404B – APRIL 1998 – REVISED DECEMBER 2000 D D D D D D D D description LV161A . . . J OR W PACKAGE LV161A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW CLR CLK A B C D ENP GND 1 16 2

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 LV161A . . . J OR W PACKAGE LV161A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP (Output Ground Bounce)

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404E − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4 13

Contextual Info: LV161A, LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS S C L S 4 0 4 -A P R IL 1998 EPIC Enhanced-Performance Implanted CMOS Process • Typical V q lp (Output Ground Bounce) < 0.8 V at VCc, Ta = 25°C LV161A . . . J OR W PACKAGE LV161A . . . D, DB, DGV, NS, OR PW PACKAGE

A115-A

Abstract: C101 SN54LV161A SN74LV161A 74LV161A
Contextual Info: LV161A, LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404B – APRIL 1998 – REVISED DECEMBER 2000 D D D D D D D D description LV161A . . . J OR W PACKAGE LV161A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW CLR CLK A B C D ENP GND 1 16 2

74ls111

Abstract: 2SA872 spice 74LS122 spice model hitachi mosfet power amplifier audio application BC240 hitachi mosfet audio application note 74ls221 Spice 74LS123 spice 2sk2685 spice spice 74ls00
Contextual Info: INDEX GENERAL General Information Sales Locations Semiconductor Packages FLAT PANEL CONTROLLER / DRIVER Liquid Crystal Display Controller MICROCONTROLLER Microcontroller General Micro. Shortform Micro. Overview Micro. Hardware Manual Micro. Program. Manual

Contextual Info: LV161A, LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404 – APRIL 1998 description The ’LV161A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V VCC operation. These synchronous, presettable counters feature an internal carry look-ahead for application in

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4