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    M54HC112 Search Results

    M54HC112 Datasheets (7)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    M54HC112 STMicroelectronics RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Original PDF
    M54HC112 STMicroelectronics DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Original PDF
    M54HC112D STMicroelectronics RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Original PDF
    M54HC112F1 SGS-Thomson DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Scan PDF
    M54HC112F1 STMicroelectronics DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Scan PDF
    M54HC112F1R STMicroelectronics DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Original PDF
    M54HC112K STMicroelectronics RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Original PDF

    M54HC112 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    74hc112

    Abstract: No abstract text available
    Text: M54HC112 M74HC112 SCSTHOMSON m DUAL J-K FLIP FLOP WITH PRESET AND CLEAR a HIGH SPEED fMAX = 59 MHz Typ. at VCC= 5V LOW POWER DISSIPATION lCC = 2 (iA at Ta = 25°C • HIGH NOISE IMMUNITY VNIH = VNIL= 28% Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS


    OCR Scan     		M54HC112 M74HC112 54/74LS112 M54/74HC112 M54HC112/M74HCis M54/74HC112 74hc112 PDF

    IC 74HC112

    Abstract: H74HC112 74LS112 J-K flip flop clock inputs 54HC 74HC M54HC112 M74HC112 H11L 74ls112 pin diagram
    Text: HS-CMOS" INTEGRATED CIRCUITS a M54HC112 M74W112 4 147 z /~ P R E L IM IN AmRVY Di DATA DUAL J-K FLIP FLOP W ITH PRESET AND CLEAR DESCRIPTION The M 5 4 /7 4 H C 1 12 is the high speed C M O S DUAL J-K FL IP -F L O P W IT H P R E S E T A N D C LE A R fabricated in silicon ga te C 2M O S technology. It


    OCR Scan     		M54HC112 H74HC112 M54/74HC112 M54HC112/M74HC112 IC 74HC112 H74HC112 74LS112 J-K flip flop clock inputs 54HC 74HC M54HC112 M74HC112 H11L 74ls112 pin diagram PDF

    TF311

    Abstract: JK flip flop IC JK flip flop IC diagram M54HC112 M54HC112D M54HC112K
    Text: M54HC112 RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 79MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:


    Original     		M54HC112 79MHz SCC-9203-051 FPC-16 M54HC112D M54HC112K M54HC112D1 TF311 JK flip flop IC JK flip flop IC diagram M54HC112 M54HC112D M54HC112K PDF

    74HC112 pin diagram

    Abstract: 74ls112 function table 74HC112
    Text: M54HC112 M74HC112 SGS-THOMSON G L ì[LI TF[^ 5 RQ0© i DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIGH SPEED fMAX= 59 MHz (Typ.) at VCC= 5V LOW POWER DISSIPATION Icc = 2 at TA = 25°C ■ HIGH NOISE IMMUNITY V nih = V Nil = 28% Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY


    OCR Scan     		M54HC112 M74HC112 M74HC112 54/74LS112 M54/74HC112 M54/74HC112 74HC112 pin diagram 74ls112 function table 74HC112 PDF

    M54HC112

    Abstract: M54HC112D M54HC112K
    Text: M54HC112 RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 79MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:


    Original     		M54HC112 79MHz SCC-9203-051 M54HC112 M54HC112D M54HC112K PDF

    74HC112

    Abstract: 74LS112 JK EDGE TRIGGERED FLIP FLOP
    Text: f Z T SGS-THOMSON ^ 7 # « [fM L E O ïM K S M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . HIGHSPEED fMAX = 67 MHz TYP. AT Vcc = 5 V • LOW POWER DISSIPATION Ice = 2 |jA AT T a = 25 ’C ■ HIGH NOISE IMMUNITY V nih = V n il = 28 % V c c (MIN.)


    OCR Scan     		M54HC112 M74HC112 54/74LS112 M54/74HC112 74HC112 74LS112 JK EDGE TRIGGERED FLIP FLOP PDF

    IC 74HC112

    Abstract: JK flip flop IC diagram 74LS112 JK EDGE TRIGGERED FLIP FLOP 74ls112 pin diagram 74ls112 function table 74HC112 Toggle flip flop IC M54HC112 M54HC112F1R M74HC112
    Text: M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 67 MHz TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS


    Original     		M54HC112 M74HC112 54/74LS112 M54HC112F1R M74HC112M1R M74HC112B1R M74HC112C1R M54/74HC112 IC 74HC112 JK flip flop IC diagram 74LS112 JK EDGE TRIGGERED FLIP FLOP 74ls112 pin diagram 74ls112 function table 74HC112 Toggle flip flop IC M54HC112 M54HC112F1R M74HC112 PDF

    74HC112 pin diagram

    Abstract: 74hc112 IC 74HC112 74ls112 waveform 74HC74 54HC 74HC M54HC112 M54HC112F1 M74HC112
    Text: M54HC112 M74HC112 S G S -T H O M S O N K * [ f 3 HkHOT®üao S DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIGH SPEED fMAX= 59 MHz Typ. at V c c = 5V LOW POWER DISSIPATION Ic c = 2 /iA at TA = 25 °C ■ HIGH NOISE IM M U NITY V n IH = V n i l = 28°/ o VCC (MIN.)


    OCR Scan     		M54HC112 M74HC112 54/74LS112 M54/74HC112 M54HC112/M74HC112 M54/74HC112 K50V- 74HC112 pin diagram 74hc112 IC 74HC112 74ls112 waveform 74HC74 54HC 74HC M54HC112F1 M74HC112 PDF

    Untitled

    Abstract: No abstract text available
    Text: SbE D • 7 * ^ 2 3 7 OGB'îflm 2S7 ■ S G T H S G S -T H O M S O N M 5 4 H C Ï 12 LiOT KDD i M 7 4 H C 1 12 6 S-THOMSON ’T-HÙ-ÔT-OT DUAL J-K FLIP FLOP WITH PRESET AND CLEAR ■ HIGH SPEED fMAX = 59 MHz (Typ. at VCC= 5V LOW POWER DISSIPATION Ice = 2 jiA at TA = 25°C


    OCR Scan     		280/o 54/74LS112 74HC112 S-10216 PDF

    Untitled

    Abstract: No abstract text available
    Text: / = T ^ 7# M 5 4 H C 1 12 M 7 4 H C 1 12 S G S -T H O M S O N ü M tM U liO T O K S DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIGH SPEED fMAX = 67 MHz TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 2 |aA AT T a = 25 "C ■ HIGH NOISE IMMUNITY Vnih = Vnil = 28 % Vcc (MIN.)


    OCR Scan     		54/74LS112 M54HC112F1R M74HC112B1R M54/74H M54/M74HC112 PDF