verilog code for serial transmitter
Abstract: 3.125G verilog prbs generator N1 ASIC
Text: SERDES Framer Interface Level-5 OIF Compliant SFI-5 Source Synchronous Interface Macro Transmitter Macro Structure Receiver Macro Structure TX Hard Macro n=16 n=15 Up to 3.125Gbps x 17-ch TXOn (n=0-16) n=1 n=0 Data Unit 16:1 MUX RX (Hard Macro) (Soft Macro)
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125Gbps
17-ch
195Mbps
256-bits
156M-195MHz
622M-781MHz
verilog code for serial transmitter
3.125G
verilog prbs generator
N1 ASIC
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MRF837
Abstract: No abstract text available
Text: MRF837 RF & MICROWAVE DISCRETE LOW POWER TRANSISTORS Features • Specified @ 12.5V, 870 MHz characteristics • Output Power = 750 mW • Minimum Gain = 8.0dB • Efficiency 60% Typical • Cost Effective Macro-X package DESCRIPTION: Macro X Designed primarily for wideband large signal stages in
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MRF837
870MHz,
MRF837
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SFI4
Abstract: sfi4.1 SFI-4 fujitsu lvds standard OC192
Text: SERDES Framer Interface Level-4 OIF Compliant SFI-4 Source Synchronous Interface Macro ASIC 4 ODT0[3:0] Rx Macro SP 622/780 Mbps x 16ch 4 ODTn[3:0] SP OCKL 1/4 SERDES / Other Devices 622/780 MHz clock Customer Core Logic Tx Macro IDT0[3:0] IDTn[3:0] 4 PS 622/780 Mbps x 16ch
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16-channel
780Mbps
ASIC-FS-20935-6/2002
SFI4
sfi4.1
SFI-4
fujitsu lvds standard
OC192
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rr8 ge
Abstract: LT 612 16421 R255
Text: ST9+ 8-BIT MCUs GNU toolchain TR9 MACRO-EXPANDER and GAS9 ASSEMBLER USER MANUAL For Toolchain 4.x November 1998 1 ST9+ 8-BIT MCUs GNU Toolchain TR9 MACRO-EXPANDER & GAS9 ASSEMBLER USER MANUAL For Toolchain 4.x November 1998 Ref: DOC-ST9XXX-TR9/GAS9 1 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED.
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Batron bt
Abstract: BT11608
Text: 36 BATRON 8 mm Character Height LCD Modules - MACRO LINE BT 11608 Character LCD Modules 1 Line x 16 Characters Dimensions [mm] Dot Size • MECHANICAL DATA ■ PIN TABLE Parameter Width x Height x Depth Unit Pin Symbol Signal Description Outline Dimensions
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Batron bt 42008
Abstract: 20 x 04 character lcd 42008 bt 42008 bt 146 led matrix 8 x 16 driver Batron bt Batron 5x7 matrix input output Batron LCD Application notes
Text: 42 BATRON 8 mm Character Height LCD Modules - MACRO LINE BT 42008 Character LCD Modules 4 Lines x 20 Characters Dimensions [mm] Dot Size • MECHANICAL DATA ■ PIN TABLE Parameter Width x Height x Depth Unit Pin Symbol Signal Description Outline Dimensions
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8 x 8 DOT MATRIX LED DISPLAY driver
Abstract: BT10809 display connector 5x7 DOT MATRIX LcD DISPLAY DRIVER LCD DISPLAY UNIT
Text: 44 BATRON 9 mm Character Height LCD Modules - MACRO LINE BT 10809 Character LCD Modules 1 Line x 8 Characters Dimensions [mm] Dot Size • MECHANICAL DATA ■ PIN TABLE Parameter Width x Height x Depth Unit Pin Symbol Signal Description Outline Dimensions
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Batron BT 21608 VSS 05
Abstract: Batron bt 21608 Batron bt Batron bt 21608 VSS-01 Batron BT 21608 VSS
Text: 38 BATRON 8 mm Character Height LCD Modules - MACRO LINE BT 21608 Character LCD Modules 2 Lines x 16 Characters Dot Size Dimensions [mm] • MECHANICAL DATA ■ PIN TABLE Parameter Width x Height x Depth Unit Pin Symbol Signal Description Outline Dimensions
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Batron bt 22008
Abstract: BT 22008 Batron 22008 BT22008 5 mm Character Height LCD Modules LED 30 pin lcd connector led 40 to lcd 30 pin diagram
Text: BATRON 8 mm Character Height LCD Modules - MACRO LINE 39 BT 22008 Dimensions [mm] Dot Size • MECHANICAL DATA ■ PIN TABLE Parameter Width x Height x Depth Unit Pin Symbol Signal Description Outline Dimensions 146 x 43 x 10 with LED: 14 mm 1 VSS GND (0 V)
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mrf9411
Abstract: MMBR941
Text: MMBR941/MRF9411 NPN SILICON LOW NOISE, HIGH-FREQUENCY Features • Specified @ 12.5V, 870 MHz characteristics • Output Power = 750 mW • Minimum Gain = 8.0dB • Efficiency 60% Typical • Cost Effective Macro-X package DESCRIPTION: Designed primarily for wideband large signal stages in
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MMBR941/MRF9411
870MHz,
mrf9411
MMBR941
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MRF837
Abstract: No abstract text available
Text: MRF837 NPN SILICON RF LOW POWER TRANSISTOR DESCRIPTION: PACKAGE STYLE MACRO-X The ASI MRF837 is Designed primerily for wideband large signal predriver stages in 800 MHz and UHF frequency ranges. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.44 5.21 0.175 0.205
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MRF837
MRF837
mW/870
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MRF559
Abstract: No abstract text available
Text: MRF559 RF & MICROWAVE DISCRETE LOW POWER TRANSISTORS Features • • • • • • Specified @ 12.5 V, 870 MHz Characteristics Output Power = .5 W Minimum Gain = 8.0 dB Efficiency 50% Cost Effective Macro X Package Electroless Tin Plated Leads for Improved Solderability
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MRF559
MRF545
MRF544
MRF559
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MRF559
Abstract: No abstract text available
Text: MRF559 RF & MICROWAVE DISCRETE LOW POWER TRANSISTORS Features • • • • • • Specified @ 12.5 V, 870 MHz Characteristics Output Power = .5 W Minimum Gain = 8.0 dB Efficiency 50% Cost Effective Macro X Package Electroless Tin Plated Leads for Improved Solderability
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MRF559
MRF559
3-20-0erves
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MRF941
Abstract: No abstract text available
Text: MRF941 RF & MICROWAVE DISCRETE LOW POWER TRANSISTORS Features • Fully Implanted Base and Emitter Structure. • High Gain, GNF = 15 dB @ 1 GHz • Low Noise Figure – 1.3dB @ 1GHz • Ftau - 8.0 GHz @ 6v, 15mA • Cost Effective Macro X Package DESCRIPTION:
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MRF941
MRF941
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MRF559
Abstract: No abstract text available
Text: MRF559 RF & MICROWAVE DISCRETE LOW POWER TRANSISTORS MRF559G * G Denotes RoHS Complaint, Pb Free Terminal Finish Features • • • • • • Specified @ 12.5 V, 870 MHz Characteristics Output Power = .5 W Minimum Gain = 8.0 dB Efficiency 50% Cost Effective Macro X Package
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MRF559
MRF559G
MRF559
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Verilog DDR memory model
Abstract: Fast Cycle RAM FCRAM FCRAM-Controller FOIP verilog ARC processor
Text: Synthesizable High Performance TM FCRAM Controller CONTROLLER UNIT HOST INTERFACE UNIT I/O Cells Custom Bus Interface Generic Bus Interface FCRAM Controller Macro I/O Cells CL CLK PD CS F A0-A14 B0-B14 Memory Interface 4 x 8M x 8 FCRAM DQ0-DQ7 DQS DQS Vdd
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A0-A14
B0-B14
ASIC-FS-20879-09/2001
Verilog DDR memory model
Fast Cycle RAM
FCRAM
FCRAM-Controller
FOIP
verilog ARC processor
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MRF951
Abstract: 2N4427 2N5109 2N5179 2N6255 MRF4427 MRF553 MRF5943C MRF607
Text: MRF951 RF & MICROWAVE DISCRETE LOW POWER TRANSISTORS Features • Fully Implanted Base and Emitter Structure. • High Gain, Gain at Optimum Noise Figure = 14 dB @ 1 GHz • Low Noise Figure – 1.3dB @ 1GHz • Ftau - 8.0 GHz @ 6v, 30mA • Cost Effective Macro X Package
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MRF951
MRF4427,
2N4427
MRF553
MRF553T
MRF607
2N6255
2N5179
MRF951
2N4427
2N5109
2N5179
2N6255
MRF4427
MRF553
MRF5943C
MRF607
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Comparators
Abstract: ttl to cmos converter sarnoff
Text: 8-Bit, 60 MSPS 145 mW Flash A/D Converter Macro Cell 53 x 49 mils, 1.3mm x 1.2mm 1.0µDLM FEATURES • Industry standard 1.0 Micron CMOS Digital Processing; Operational to 5.0 Volts VDD • Flashing Type ADC • TTL Inputs; CMOS or TTL Outputs • Tri-State Output Buffers with Enable
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atmel 306
Abstract: ATMEL 529 atmel 228 atmel 334 atmel 438 AT40K AT40KAL AT94K mps16
Text: IP Core Generator: Multiplier Features • • • • • • • • • • • Multiplier – Serial Parallel Multiplier – Signed Multiplier – Signed, Pipeline x 1 Multiplier – Unsigned Multiplier – Unsigned, Pipeline x 1 Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for
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AT94K
12/01/xM
atmel 306
ATMEL 529
atmel 228
atmel 334
atmel 438
AT40K
AT40KAL
mps16
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GLT44032-E
Abstract: No abstract text available
Text: GLT44032-E 128K x 32 Embedded EDO DRAM Macro FEATURES ◆ Logical organization: 128Kx32 bits ◆ Physical organization: 512x256x32 ◆ Single 3.3v ± 0.3v power supply ◆ 512-cycle refresh in 8 ms ◆ Refresh modes: RAS only, CBR, and Hidden ◆ Single CAS with 4 DQM for Byte Write control
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GLT44032-E
128Kx32
512x256x32
512-cycle
GLT44032-E
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Untitled
Abstract: No abstract text available
Text: GLT44032-E 128K x 32 Embedded EDO DRAM Macro FEATURES ◆ Logical organization: 128Kx32 bits ◆ Physical organization: 512x256x32 ◆ Single 3.3v ± 0.3v power supply ◆ 512-cycle refresh in 8 ms ◆ Refresh modes: RAS only, CBR, and Hidden ◆ Single CAS with 4 DQM for Byte Write control
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GLT44032-E
128Kx32
512x256x32
512-cycle
GLT44032-E
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Untitled
Abstract: No abstract text available
Text: Signetics PLHS501 Programmable Macro Logic Random Logic Unit 32 x 72 x 24 Military Application Specific Products Product Specification PIN CONFIGURATION DESCRIPTION F EA T U R ES The P L H S 5 0 1 is a member of the Signetics Program m able M acro Logic
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OCR Scan
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PLHS501
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PEEL18CV8P-35
Abstract: PEEL18CV8P-25
Text: INTERNATIONAL CMOS TECHNOLOGY INC. March 1989 Features ADVANCED CMOS EEPROM TECHNOLOGY ARCHITECTURAL FLEXIBILITY — 74 Product Term X 36 Input array — Up to 18 Inputs and 8 I/O pins — Independently configurable I/O macro cells: polarity, register, combinatorial, bi-directional
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18CV825
Abstract: No abstract text available
Text: ET , INC. PEEL 18CV8-25 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility — 74 product term x 36 input array — Up to 18 inputs and 8 I/O pins — Independent configurable I/O macro cells — Synchronous preset, asynchronous clear
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18CV8-25
18CV825
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