MACROS IN EMBEDDED COMPUTING Search Results

MACROS IN EMBEDDED COMPUTING Result Highlights (5)

Part	Manufacturer	Description	Download
CS-VHDCIMX200-003	Amphenol Cables on Demand	Amphenol CS-VHDCIMX200-003 VHDCI SCSI (SCSI-5) LVD/SE Cable - .8mm 68-pin VHDCI SCSI Male to Male 3m	Datasheet
CS-VHDCIMX200-000.5	Amphenol Cables on Demand	Amphenol CS-VHDCIMX200-000.5 VHDCI SCSI (SCSI-5) LVD/SE Cable - .8mm 68-pin VHDCI SCSI Male to Male .5m	Datasheet
CS-VHDCIMX200-005	Amphenol Cables on Demand	Amphenol CS-VHDCIMX200-005 VHDCI SCSI (SCSI-5) LVD/SE Cable - .8mm 68-pin VHDCI SCSI Male to Male 5m	Datasheet
CS-VHDCIMX200-006	Amphenol Cables on Demand	Amphenol CS-VHDCIMX200-006 VHDCI SCSI (SCSI-5) LVD/SE Cable - .8mm 68-pin VHDCI SCSI Male to Male 6m	Datasheet
CS-VHDCIMX200-001	Amphenol Cables on Demand	Amphenol CS-VHDCIMX200-001 VHDCI SCSI (SCSI-5) LVD/SE Cable - .8mm 68-pin VHDCI SCSI Male to Male 1m	Datasheet

MACROS IN EMBEDDED COMPUTING Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
TF-680 Abstract: L302 FV09 macros in embedded computing Text: DATA SHEET QB-8 / QB-8E 3.3 Volt , 0.44-Micron Gate-Array Description NEC’s 3.3V QB-8 family consists of ultra-high performance, sub-micron gate arrays, targeted for applications requiring high speeds and low power dissipation. The QB-8 family offers not	Original	44-Micron TF-680 L302 FV09 macros in embedded computing	PDF
CE61 Abstract: 032UW 8 bit array multiplier of BGA Staggered Pins package Text: CE61 Series Embedded Array ▼ 0.28µm Leff Features 0.28µm Leff 0.35µm drawn Propagation delay of 85 ps Mixed-signal macros–A/D and D/A converters High density diffused RAMs and ROMs Separate core and I/O supply voltages I/Os–5V, 3.3V and 5V tolerant	Original	E9/15/19/25/35/45/59/71, F20/30/40/50/60/70/80 E15/19/25/35/45/58/71, F30/40/50/60/70/80 F40/50/60/70/80 E35/45/59/71, F50/60/70/80 E19/25/35/45/59/71 E15/19, F40/50 CE61 032UW 8 bit array multiplier of BGA Staggered Pins package	PDF
Untitled Abstract: No abstract text available Text: CE61 Series Embedded Array ▼ 0.28µm Leff Features 0.28µm Leff 0.35µm drawn Propagation delay of 85 ps Mixed-signal macros–A/D and D/A converters High density diffused RAMs and ROMs Separate core and I/O supply voltages I/Os–5V, 3.3V and 5V tolerant	Original	high9/71, F20/30/40/50/60/70/80 E15/19/25/35/45/58/71, F30/40/50/60/70/80 F40/50/60/70/80 E35/45/59/71, F50/60/70/80 E19/25/35/45/59/71 E15/19, F40/50	PDF
MSS30 Abstract: CE71 CE71J1 CE71J2 CE71J3 dual lvds vhdl fujitsu lvds standard Text: CE71 Series Embedded Array t 0.25µm CMOS Technology Features 0.18µm Leff 0.24µm drawn Propagation delay of 61 ps Separate core and I/O supply voltages Mixed-signal macros–A/D and D/A converters I/Os: 2.5V, 3.3V, 5V tolerant Core power supply voltage: 2.5V, 1.8V, 1.5V	Original	ASIC-FS-20655-11/99 MSS30 CE71 CE71J1 CE71J2 CE71J3 dual lvds vhdl fujitsu lvds standard	PDF
"Single-Port RAM" Abstract: CE71 CE71J1 CE71J2 CE71J3 tb 304 Text: CE71 Series Embedded Array t 0.25µm CMOS Technology Features 0.18µm Leff 0.24µm drawn Propagation delay of 61 ps Separate core and I/O supply voltages Mixed-signal macros–A/D and D/A converters I/Os: 2.5V, 3.3V, 5V tolerant Core power supply voltage: 2.5V, 1.8V, 1.5V	Original	ASIC-FS-20655-11/99 "Single-Port RAM" CE71 CE71J1 CE71J2 CE71J3 tb 304	PDF
AT91EB55 Abstract: ML674001 TMS470 The ARM7TDMI Debug Architecture LPC210X TMS470R1B1M flash Unicoi Systems Text: ARM IAR Embedded Workbench® IDE User Guide for Advanced RISC Machines Ltd’s ARM Cores UARM-12 COPYRIGHT NOTICE Copyright 1999–2006 IAR Systems. All rights reserved. No part of this document may be reproduced without the prior written consent of IAR	Original	UARM-12 writeMemory16 writeMemory32 AT91EB55 ML674001 TMS470 The ARM7TDMI Debug Architecture LPC210X TMS470R1B1M flash Unicoi Systems	PDF
MSP430 IAR Embedded Workbench ide Abstract: MSP430 MSP430F149 MSP-FET430X110 P120 P140 P410 P440 MSP430 IAR Embedded Workbench ide user guide MSP430 General Purpose Subroutines Text: MSP430 IAR Embedded Workbench IDE User Guide for Texas Instruments’ MSP430 Microcontroller Family U430-5 COPYRIGHT NOTICE Copyright 1996–2006 IAR Systems. All rights reserved. No part of this document may be reproduced without the prior written consent of IAR	Original	MSP430 U430-5 writeMemory16 writeMemory32 20-bit MSP430 IAR Embedded Workbench ide MSP430F149 MSP-FET430X110 P120 P140 P410 P440 MSP430 IAR Embedded Workbench ide user guide MSP430 General Purpose Subroutines	PDF
tab 207k Abstract: SD host controller vhdl CE81 689K arm A8 qfp QAM verilog oak dsp core i3 i5 i7 8394K Text: CE81 Series Embedded Array ▼ 0.18µm CMOS Technology Features ▼ • • • • • • • • • • • • • • 0.13µm effective channel length 3 to 5 layers of metal interconnects Very high-density: 86K raw gates/mm2 Up to 23 million gates Core power supply voltage: 1.8V to 1.1V	Original	ASIC-FS-20819-10/99 tab 207k SD host controller vhdl CE81 689K arm A8 qfp QAM verilog oak dsp core i3 i5 i7 8394K	PDF
HC335FF1152 Abstract: HC325FF780 HC335 EP3SE110F1152 EP3SE110F Text: Section I. Device Core This section provides a complete overview of all features relating to the HardCopy III device family. HardCopy III devices are Altera’s latest generation of low-cost, high-performance, low power ASICs with pin-outs, densities, and	Original		PDF
LF1152 Abstract: EP4SE360 ep4sgx180 EP4SGX290 EP4SGX360 EP4SGX70 HIV51001-2 EP4SE530H35 "Stratix IV" Package layout footprint HC4GX35 Text: Section I. Device Core This section provides a complete overview of all features relating to the HardCopy IV device family. HardCopy IV devices are Altera’s latest generation of low-cost, high-performance, low power ASICs with pin-outs, densities, and	Original		PDF
NAND Flash Programmer with TSOP-48 adapter Abstract: INTEL Core i7 860 schematic diagram inverter lcd monitor fujitsu MB506 ULTRA HIGH FREQUENCY PRESCALER fujitsu LVDS vga MB89625R VHDL code simple calculator of lcd display JTag Emulator MB90F497 Millbrook BGA TBA 129-5 Text: Master Product Selector Guide February 2001 Fujitsu Microelectronics, Inc. Contents Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Application Specific ICs ASICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3	Original		PDF
JD 1804 Abstract: CS71 Text: CS71 Series Standard Cell t 0.25µm CMOS Technology Features t • 0.18µm Leff 0.24µm drawn • Up to 10 million gates • 0.05µW/gate/MHz power dissipation • 2.5V, 3.3V, 5V tolerant I/O options • Special high-performance I/Os–PCML, LVDS, PCI, SSTL, GTL+, AGP, USB	Original	ASIC-FS-20690-11/99 JD 1804 CS71	PDF
CS71 Abstract: No abstract text available Text: CS71 Series Standard Cell t 0.25µm CMOS Technology Features t • 0.18µm Leff 0.24µm drawn • Up to 10 million gates • 0.05µW/gate/MHz power dissipation • 2.5V, 3.3V, 5V tolerant I/O options • Special high-performance I/Os–PCML, LVDS, PCI, SSTL, GTL+, AGP, USB	Original	ASIC-FS-20690-11/99 CS71	PDF
adc verilog Abstract: CS71 Text: CS71 Series Standard Cell ▼ 0.25µm CMOS Technology Features ▼ • 0.18µm Leff 0.24µm drawn • Up to 10 million gates • 0.05µW/gate/MHz power dissipation • 2.5V, 3.3V, 5V tolerant I/O options • Special high-performance I/Os–PCML, LVDS, PCI, SSTL, GTL+, AGP, USB	Original	ASIC-FS-20690-11/99 adc verilog CS71	PDF

ieee floating point vhdl Abstract: floating point verilog ieee floating point verilog APEX20K APEX20KC APEX20KE FLEX10KE IEEE-754 Text: DINT2FP Integer to Floating Point Pipelined Converter ver 2.32 OVERVIEW The DINT2FP is the pipelined integer to floating point converter. The input and output numbers format is according to IEEE-754 standard. DINT2FP supports double word integers 4 Bytes and single precision real	Original	IEEE-754 IEEE-754 FLEX10KE APEX20K APEX20KE APEX20KC ieee floating point vhdl floating point verilog ieee floating point verilog APEX20K APEX20KC APEX20KE FLEX10KE	PDF
ieee floating point multiplier vhdl Abstract: ieee floating point multiplier verilog vhdl code for floating point multiplier FLEX10KE IEEE754 IEEE-754 APEX20K APEX20KC APEX20KE vhdl code complex multiplier Text: DFPMUL Floating Point Pipelined Multiplier Unit ver 2.70 OVERVIEW The DFPMUL uses the pipelined mathematics algorithm to multiply two arguments. The input numbers format is according to IEEE754 standard. DFPMUL supports single precision real number. Multiply operation was	Original	IEEE754 IEEE-754 ieee floating point multiplier vhdl ieee floating point multiplier verilog vhdl code for floating point multiplier FLEX10KE APEX20K APEX20KC APEX20KE vhdl code complex multiplier	PDF
MBF310 Abstract: plasma tv technology ic fujitsu bubble memory diagram circuit usb mp3 player with radio fm lcd optical fingerprint sensor major project for electronics and communication e FR60Lite biosensor CMOS image sensor fingerprint circuit circuit diagram of queuing with LCD display Text: F a l l 2 0 0 3 Fujitsufocus The News on the Latest Semiconductor Technologies and Products from Fujitsu Microelectronics America, Inc. The World’s First Single-chip 10Gbps Ethernet Switch The new 10Gbps Ethernet switch chip was developed for the optical network,	Original	10Gbps 10Gbps 12-port, 32-bit CORP-NL-20988-10/2003 MBF310 plasma tv technology ic fujitsu bubble memory diagram circuit usb mp3 player with radio fm lcd optical fingerprint sensor major project for electronics and communication e FR60Lite biosensor CMOS image sensor fingerprint circuit circuit diagram of queuing with LCD display	PDF
vhdl code of floating point unit Abstract: ieee floating point vhdl digital clock verilog code APEX20K APEX20KC APEX20KE FLEX10KE ieee floating point verilog Text: DFP2INT Floating Point To Integer Pipelined Converter ver 2.20 OVERVIEW The DFP2INT is the pipelined floating point to integer converter. The input and output numbers format is according to IEEE-754 standard. DFP2INT supports single precision real numbers and double word integers 4	Original	IEEE-754 APEX20K APEX20KE APEX20KC vhdl code of floating point unit ieee floating point vhdl digital clock verilog code APEX20K APEX20KC APEX20KE FLEX10KE ieee floating point verilog	PDF
vhdl code of floating point adder Abstract: verilog code for floating point adder vhdl code of pipelined adder ieee 754 vhdl code of floating point adder vhdl code for floating point adder verilog code for floating point unit ieee floating point vhdl IEEE754 digital clock vhdl code IEEE-754 Text: DFPADD Floating Point Pipelined Adder Unit ver 2.50 OVERVIEW The DFPADD uses the pipelined mathematics algorithm to compute sum of two arguments. The input numbers format is according to IEEE-754 standard. DFPADD supports single precision real number. Add operation	Original	IEEE-754 IEEE754 vhdl code of floating point adder verilog code for floating point adder vhdl code of pipelined adder ieee 754 vhdl code of floating point adder vhdl code for floating point adder verilog code for floating point unit ieee floating point vhdl digital clock vhdl code	PDF
APEX20K Abstract: APEX20KC APEX20KE FLEX10KE verilog code for floating point unit vhdl code of floating point unit digital clock vhdl code IEEE-754 digital clock verilog code Text: DFPSQRT Floating Point Pipelined Square Root Unit ver 2.90 OVERVIEW The DFPSQRT uses the pipelined mathematics algorithm to compute square root function. The input number format is according to IEEE-754 standard. DFPSQRT supports single precision real numbers. SQRT	Original	IEEE-754 APEX20K APEX20KC APEX20KE FLEX10KE verilog code for floating point unit vhdl code of floating point unit digital clock vhdl code digital clock verilog code	PDF
vhdl code for Clock divider for FPGA Abstract: verilog code divide floating point verilog verilog code for floating point unit IEEE-754 vhdl code of floating point unit APEX20K APEX20KC APEX20KE FLEX10KE Text: DFPDIV Floating Point Pipelined Divider Unit ver 2.15 OVERVIEW The DFPDIV uses the pipelined mathematics algorithm to divide two arguments. The input numbers format is according to IEEE754 standard. DFPDIV supports single precision real number. Divide operation was pipelined up to 15 levels. Input data are fed every	Original	IEEE754 IEEE-754 IEEE-754 vhdl code for Clock divider for FPGA verilog code divide floating point verilog verilog code for floating point unit vhdl code of floating point unit APEX20K APEX20KC APEX20KE FLEX10KE	PDF
SA-27E Abstract: IBM PCI Express serdes architecture Text: Standard cell/gate array ASIC for mainstream and cost-sensitive applications requiring fast time-to-market SA-27E ASIC Highlights Integration and performance deliver exceptional value. The IBM SA-27E ASIC is a dense,        • Gate delay: 33 picoseconds	Original	SA-27E SA14-2183-03 IBM PCI Express serdes architecture	PDF
0.18-um CMOS technology characteristics Abstract: NEC 71055 NEC V30MX DSPG 71055 STEPS 30175 V30MX VR10000 A1246 CMOS-10 Text: DATA SHEET PRODUCT LETTER CB-C10 2.5 Volt 0.25-Micron CMOS Cell-Based ASIC PRELIMINARY Figure 1. Chip Size Package CSP Description NEC’s 0.25 µm (0.18 µm eff.) CB-C10 family incorporates ultra-high performance, deep submicron cell-based ASIC’s for high-end	Original	CB-C10 25-Micron CB-C10 GB-MK14 0.18-um CMOS technology characteristics NEC 71055 NEC V30MX DSPG 71055 STEPS 30175 V30MX VR10000 A1246 CMOS-10	PDF
D78 NEC Abstract: 986M Text: CB-C10 2.5-Volt, 0.25-M icron drawn CMOS Cell-Based ASIC NEC NEC Electronics Inc. Preliminary March 1997 Figure 1. Chip Size Package (CSP) Description NEC’s 0.25 n.m drawn (0.18 (j.mL-effective)CB-C10family incorporates ultra-high-performance cores with deep sub	OCR Scan	CB-C10 CB-C10family D78 NEC 986M	PDF

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MACROS IN EMBEDDED COMPUTING Search Results

MACROS IN EMBEDDED COMPUTING Result Highlights (5)

MACROS IN EMBEDDED COMPUTING Datasheets Context Search

TF-680

CE61

Untitled

MSS30

"Single-Port RAM"

AT91EB55

MSP430 IAR Embedded Workbench ide

tab 207k

HC335FF1152

LF1152

NAND Flash Programmer with TSOP-48 adapter

JD 1804

CS71

adc verilog

ieee floating point vhdl

ieee floating point multiplier vhdl

MBF310

vhdl code of floating point unit

vhdl code of floating point adder

APEX20K

vhdl code for Clock divider for FPGA

SA-27E

0.18-um CMOS technology characteristics

D78 NEC