MC10EP196FAR2 Search Results

MC10EP196FAR2 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
MC10EP196FAR2		On Semiconductor	3.3V/5V ECL Programmable Delay Chip with FTUNE		Original	PDF

MC10EP196FAR2 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the	Original	PDF	MC10EP196, MC100EP196 MC10/100EP196 EP195 EP196 r14525 MC10E196/D
TQFP 100 socket Abstract: No abstract text available Text: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the	Original	PDF	MC10EP196, MC100EP196 MC10/100EP196 EP195 EP196 r14525 MC10EP196/D TQFP 100 socket
motorola HEP cross reference Abstract: EPT 4045 KPT23 motorola HEP 320 cross reference vef 202 manual KEP52 MC10EP016 HEP 801 hep51 HEP64 Text: BR1513/D Rev. 2, Apr-2001 ECLinPS Plus Device Data ECLinPS Plus Device Data Advanced ECL in Picoseconds BR1513/D Rev. 2, Apr–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved” ECLinPS, ECLinPS Lite, and ECLinPS Plus are trademarks of Semiconductor Components Industries, LLC.	Original	PDF	BR1513/D Apr-2001 r14525 DLD601 motorola HEP cross reference EPT 4045 KPT23 motorola HEP 320 cross reference vef 202 manual KEP52 MC10EP016 HEP 801 hep51 HEP64
MC100EP196 Abstract: MC100EP196FA MC100EP196FAR2 MC10EP196 MC10EP196FA MC10EP196FAR2 Text: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the	Original	PDF	MC10EP196, MC100EP196 MC10/100EP196 EP195 EP196 r14525 MC10EP196/D MC100EP196 MC100EP196FA MC100EP196FAR2 MC10EP196 MC10EP196FA MC10EP196FAR2
MC10EP196FA Abstract: 10000 series of ECL gates ic 4440 circuit diagram MC100EP196 MC100EP196FA MC100EP196FAR2 MC10EP196 MC10EP196FAR2 Text: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the	Original	PDF	MC10EP196, MC100EP196 MC10/100EP196 EP195 EP196 r14525 MC10E196/D MC10EP196FA 10000 series of ECL gates ic 4440 circuit diagram MC100EP196 MC100EP196FA MC100EP196FAR2 MC10EP196 MC10EP196FAR2