ug384
Abstract: CQ 346 vhdl code for spartan 6 ternary content addressable memory VHDL SPARTAN 6 structure of clb MC31 SRL16 DPRAM DSP48A1
Text: Spartan-6 FPGA Configurable Logic Block User Guide UG384 v1.1 February 23, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the
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UG384
ug384
CQ 346
vhdl code for spartan 6
ternary content addressable memory VHDL
SPARTAN 6
structure of clb
MC31
SRL16
DPRAM
DSP48A1
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RAM32M
Abstract: RAM64X1D SRLC32E RAM128X1D RAM256X1S SRL32 RAM64M ROM64x1 XC6VLX75T ROM256x1
Text: Virtex-6 FPGA Configurable Logic Block User Guide Virtex-6 FPGA CLB [optional] UG364 v1.1 September 16, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development
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UG364
RAM32M
RAM64X1D
SRLC32E
RAM128X1D
RAM256X1S
SRL32
RAM64M
ROM64x1
XC6VLX75T
ROM256x1
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XC7336
Abstract: XC7336Q mc35i PC44 XC7336-5 XC7336-15 X3339 36-Macrocell X5695 mc35
Text: XC7336/XC7336Q 36-Macrocell CMOS CPLD June 1, 1996 Version 1.0 Product Specification Features General Description • The XC7336 is a high performance CPLD providing general purpose logic integration. It consists of four PAL-like 24V9 Fast Function Blocks interconnected by the 100%populated Universal Interconnect Matrix (UIM ). See
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XC7336/XC7336Q
36-Macrocell
XC7336
XC7336Q
44-Pin
XC7336
mc35i
PC44
XC7336-5
XC7336-15
X3339
X5695
mc35
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PC84
Abstract: PQ100 XC7372 XC7372-12
Text: XC7372 72-Macrocell CMOS CPLD June 1, 1996 Version 1.0 Product Specification Features tion Blocks are turned off and unused macrocells in used Function Blocks are configured for low power operation. • • • • • • • • • • • • •
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XC7372
72-Macrocell
18-bit
68-Pin
84-Pin
PQ100
100-Pin
PQ100
PC84
XC7372
XC7372-12
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Untitled
Abstract: No abstract text available
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor October 2007 FEATURES The HI-6110 may be configured as a Bus Controller BC , a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store
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HI-6110
MIL-STD-1553
MIL-STD-1760
MIL-STD-1553B
HI-6110
MIL-STD-1553
52-PIN
52PQS
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64PCS
Abstract: No abstract text available
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor March 2007 FEATURES The HI-6110 may be configured as a Bus Controller BC , a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store
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HI-6110
MIL-STD-1553
MIL-STD-1760
MIL-STD-1553B
HI-6110
MIL-STD-1553
52-PIN
52PQS
64PCS
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holt ic 6110
Abstract: No abstract text available
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor August 2008 FEATURES The HI-6110 may be configured as a Bus Controller BC , a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store
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HI-6110
MIL-STD-1553
MIL-STD-1760
MIL-STD-1553B
HI-6110
MIL-STD-1553
52-PIN
52PQS
holt ic 6110
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holt ic 6110
Abstract: No abstract text available
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor May 2008 FEATURES The HI-6110 may be configured as a Bus Controller BC , a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store
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HI-6110
MIL-STD-1553
MIL-STD-1760
MIL-STD-1553B
HI-6110
MIL-STD-1553
52-PIN
52PQS
holt ic 6110
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str 765 RT
Abstract: No abstract text available
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor July 2006 GENERAL DESCRIPTION FEATURES The HI-6110 is a CMOS integrated circuit implementing the MIL-STD-1553 1553 data communications protocol between a host processor and a dual redundant 1553 data
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HI-6110
MIL-STD-1553
MIL-STD-1760
MIL-STD-1553B
HI-6110
MIL-STD-1553
64-PIN
52-PIN
52PQS
str 765 RT
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str 765 RT
Abstract: Holt 1553 Controller - HI6110
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor June 2006 GENERAL DESCRIPTION FEATURES The HI-6110 is a CMOS integrated circuit implementing the MIL-STD-1553 1553 data communications protocol between a host processor and a dual redundant 1553 data
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HI-6110
MIL-STD-1553
MIL-STD-1760
MIL-STD-1553B
HI-6110
MIL-STD-1553
64-PIN
52-PIN
52PQS
str 765 RT
Holt 1553 Controller - HI6110
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str 765 RT
Abstract: MIL-STD-1553-B holt ic 6110
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor September 2006 GENERAL DESCRIPTION FEATURES The HI-6110 is a CMOS integrated circuit implementing the MIL-STD-1553 1553 data communications protocol between a host processor and a dual redundant 1553 data
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HI-6110
MIL-STD-1553
MIL-STD-1760
MIL-STD-1553B
HI-6110
MIL-STD-1553
64-PIN
52-PIN
52PQS
str 765 RT
MIL-STD-1553-B
holt ic 6110
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str 765 RT
Abstract: No abstract text available
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor September 2006 GENERAL DESCRIPTION FEATURES The HI-6110 is a CMOS integrated circuit implementing the MIL-STD-1553 1553 data communications protocol between a host processor and a dual redundant 1553 data
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HI-6110
MIL-STD-1553
MIL-STD-1760
MIL-STD-1553B
HI-6110
MIL-STD-1553
64-PIN
52-PIN
52PQS
str 765 RT
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Untitled
Abstract: No abstract text available
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor October 2007 FEATURES The HI-6110 may be configured as a Bus Controller BC , a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store
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HI-6110
MIL-STD-1553
MIL-STD-1760
MIL-STD-1553B
HI-6110
MIL-STD-1553
52-PIN
52PQS
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X5650
Abstract: X5767 XC7336Q PC44 XC7300 XC7336 XC7336-10
Text: XC7336 36-Macrocell CMOS EPLD Product Specifications interconnected by the 100%-populated Universal Interconnect Matrix UIM . Features Ultra high-performance EPLD – 5 ns pin-to-pin speed on all fast inputs – 167 MHz maximum clock frequency Each Fast Function Block has 24 inputs and contains nine
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XC7336
36-Macrocell
XC7336Q
24V9ip
44-Pin
to70oC
-40oC
XC7336
PQ100
PQ160
X5650
X5767
XC7336Q
PC44
XC7300
XC7336-10
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MC3 117
Abstract: MC128 XC73108 mc103 10 pin MC124 MC116 MC92 mc11-6 PC84 PQ160
Text: XC73108 108-Macrocell CMOS CPLD June 1, 1996 Version 1.0 Product Specification Features Macrocells can individually be specified for high performance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral
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XC73108
108-Macrocell
BG225
225-Pin
PQ100
PG144
PQ160
BG225
XC73108
MC3 117
MC128
mc103 10 pin
MC124
MC116
MC92
mc11-6
PC84
PQ160
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holt ic 6110
Abstract: No abstract text available
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor February 2009 FEATURES The HI-6110 may be configured as a Bus Controller BC , a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store
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HI-6110
MIL-STD-1553
MIL-STD-1760
MIL-STD-1553B
HI-6110
MIL-STD-1553
52-PIN
52PTQS
holt ic 6110
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Holt 1553 Controller HI6110
Abstract: MIL-STD-1553 MP 1008 es Holt 1553 Controller - HI6110 HI-6110PQI HI-6110 6110 12KW HI-6110PQT 1553 bus controller
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor May 2010 FEATURES The HI-6110 may be configured as a Bus Controller BC , a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store
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HI-6110
MIL-STD-1553
MIL-STD-1760
HI-6110
16-bit
32-word
bit10
52-PIN
52PTQS
Holt 1553 Controller HI6110
MP 1008 es
Holt 1553 Controller - HI6110
HI-6110PQI
6110
12KW
HI-6110PQT
1553 bus controller
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holt ic 6110
Abstract: No abstract text available
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor March 2009 FEATURES The HI-6110 may be configured as a Bus Controller BC , a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store
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HI-6110
MIL-STD-1553
MIL-STD-1760
MIL-STD-1553B
HI-6110
MIL-STD-1553
52-PIN
52PTQS
holt ic 6110
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MP 1008 es
Abstract: MILSTD-1553 holt ic 6110
Text: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor December 2008 FEATURES The HI-6110 may be configured as a Bus Controller BC , a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store
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HI-6110
MIL-STD-1553
MIL-STD-1760
MIL-STD-1553B
HI-6110
MIL-STD-1553
52-PIN
52PTQS
MP 1008 es
MILSTD-1553
holt ic 6110
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design a 4-bit arithmetic logic unit using xilinx
Abstract: XC7272A ALU 74 x3254
Text: XC7272A 72-Macrocell CMOS CPLD June 1, 1996 Version 1.0 Product Specification Features This additional ALU in each macrocell can generate any combinatorial function of two sums of products, and it can generate and propagate arithmetic-carry signals between
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XC7272A
72-Macrocell
68-Pin
84-Pin
design a 4-bit arithmetic logic unit using xilinx
XC7272A
ALU 74
x3254
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XC7236A
Abstract: MC39I MC-13
Text: XC7236A 36-Macrocell CMOS CPLD June 1, 1996 Version 1.0 Product Specification Features This additional ALU in each macrocell can generate any combinatorial function of two sums of products, and it can generate and propagate arithmetic-carry signals between
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XC7236A
36-Macrocell
44-Pin
XC7236A
MC39I
MC-13
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XC7372
Abstract: No abstract text available
Text: HXILINX XC7372 72-Macrocell CMOS CPLD June 1 ,1 9 9 6 Version 1.0 Product Specification Features tion Blocks are turned off and unused m acrocells in used Function Blocks are configured for low power operation. • High-perform ance Com plex Program mable Logic
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OCR Scan
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XC7372
72-Macrocell
18-bit
dQ100
68-Pin
84-Pin
100-Pin
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PDF
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Untitled
Abstract: No abstract text available
Text: XC7236A 36-Macrocell CMOS EPLD HXILINX Product Specifications Features The functional versatility of the traditional programmable logic array architecture is enhanced through additional gating and control functions available in an Arithmetic Logic Unit ALU in each Macrocell. Dedicated fast arith
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XC7236A
36-Macrocell
44-Pin
XC7236A
00054bb
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Untitled
Abstract: No abstract text available
Text: f l XC7354 54-Macrocell CMOS EPLD X IL IN X Preliminary Product Specifications Features • High-Performance EPLD - 10 ns pin-to-pin delay - 100 MHz maximum clock frequency • Advanced Dual-Block architecture - Two Fast Function Blocks - Four High-Density Function Blocks
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XC7354
54-Macrocell
18-bit
68-pin
PQ160
XC7354
PG144
PG184
BG225
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