Untitled
Abstract: No abstract text available
Text: Intel Xeon Processor MP with up to 2-MB L3 Cache on the 0.13 Micron Process Datasheet Product Features • ■ ■ ■ ■ Available at 1.50, 1.90, and 2 GHz Multi-processing server support Binary compatible with applications running on previous members of the Intel®
|
Original
|
PDF
|
|
251931
Abstract: No abstract text available
Text: Intel Xeon Processor MP with up to 2-MB L3 Cache on the 0.13 Micron Process Datasheet Product Features • ■ ■ ■ ■ Available at 1.50, 1.90, and 2 GHz Multi-processing server support Binary compatible with applications running on previous members of the Intel®
|
Original
|
PDF
|
512-KB
/512K
cache/400
package/603
BX80528KL160GE
/256K
BX80532KC1500E
251931
|
xeon mp 4MB
Abstract: intel ia32 AE30 CK408 socket 615-PIN xeon mp 4MB thermal bt 690
Text: Intel Xeon Processor MP with up to 4MB L3 Cache on the 0.13 Micron Process Datasheet Product Features • ■ ■ ■ ■ Available at 1.50, 1.90, 2, 2.50, 2.80, and 3 GHz Multi-processing server support Binary compatible with applications running on previous members of the Intel®
|
Original
|
PDF
|
|
MT57V256H36P
Abstract: No abstract text available
Text: 256K x 36 2.5V VDD, HSTL, PIPELINED DDR SRAM 9Mb DDR SRAM MT57V256H36P FEATURES • • • • • • • • • • • • • • • • • • 165-Ball FBGA Fast cycle times: 5ns and 6ns 256K x 36 configuration Pipelined double data rate operation
|
Original
|
PDF
|
MT57V256H36P
165-Ball
MT57V256H36P
|
Untitled
Abstract: No abstract text available
Text: ADVANCE 256K x 36 2.5V VDD, HSTL, PIPELINED DDR SRAM 9Mb DDR SRAM MT57V256H36P FEATURES • • • • • • • • • • • • • • • • • • 165-Pin FBGA Fast cycle times: 3.3ns, 4ns, 5ns and 6ns 256K x 36 configuration Pipelined double data rate operation
|
Original
|
PDF
|
MT57V256H36P
|
Untitled
Abstract: No abstract text available
Text: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM MT54V512H18A 2-Word Burst FEATURES 165-Pin FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE
|
Original
|
PDF
|
MT54V512H18A
165-Pin
MT54V512H18A
|
Untitled
Abstract: No abstract text available
Text: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM MT54V512H18A 2-Word Burst FEATURES 165-Pin FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE
|
Original
|
PDF
|
MT54V512H18A
|
Untitled
Abstract: No abstract text available
Text: ADVANCE‡ 256K x 36 2.5V VDD, HSTL, PIPELINED DDR SRAM 9Mb DDR SRAM MT57V256H36P FEATURES • • • • • • • • • • • • • • • • • • 165-Pin FBGA Fast cycle times: 3.3ns, 4ns, 5ns and 6ns 256K x 36 configuration Pipelined double data rate operation
|
Original
|
PDF
|
MT57V256H36P
|
251931
Abstract: intel 251931 TAA 611 T12 intel 830 intel xeon 604 circuit diagram of heat sensor with fan cooling
Text: Intel Xeon Processor MP with up to 2MB L3 Cache on the 0.13 Micron Process Datasheet Product Features • ■ ■ ■ ■ Available at 1.50, 1.90, 2, 2.50, and 2.80 GHz Multi-processing server support Binary compatible with applications running on previous members of the Intel®
|
Original
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: 256K x 36 2.5V VDD, HSTL, PIPELINED DDR SRAM 9Mb DDR SRAM MT57V256H36P FEATURES • • • • • • • • • • • • • • • • • • 165-Ball FBGA Fast cycle times: 5ns and 6ns 256K x 36 configuration Pipelined double data rate operation
|
Original
|
PDF
|
MT57V256H36P
165-Ball
MT57V256H36P
|
Untitled
Abstract: No abstract text available
Text: ADVANCE 256K x 36 2.5V VDD, HSTL, PIPELINED DDR SRAM 9Mb DDR SRAM MT57V256H36P FEATURES • • • • • • • • • • • • • • • • • • 165-Pin FBGA Fast cycle times: 3.3ns, 4ns, 5ns and 6ns 256K x 36 configuration Pipelined double data rate operation
|
Original
|
PDF
|
MT57V256H36P
165-Pin
MT57V256H36P
|
Untitled
Abstract: No abstract text available
Text: 512K x 18 2.5V VDD, HSTL, QDRb4 SRAM 9Mb QDR SRAM MT54V512H18E 4-Word Burst FEATURES • 9Mb Density 512Kx18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation • High frequency operation with future migration to
|
Original
|
PDF
|
MT54V512H18E
512Kx18)
MT54V512H18E
|
Untitled
Abstract: No abstract text available
Text: 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM MT54V512H18A 2-Word Burst FEATURES 165-BALL FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation
|
Original
|
PDF
|
MT54V512H18A
165-BALL
MT54V512H18A
|
af9t
Abstract: No abstract text available
Text: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM MT54V512H18A 2-Word Burst FEATURES 165-Pin fBGA AF T • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE
|
Original
|
PDF
|
MT54V512H18A
af9t
|
|
Untitled
Abstract: No abstract text available
Text: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb4 SRAM 9Mb QDR SRAM MT54V512H18E 4-Word Burst FEATURES • 9Mb Density 512Kx18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation
|
Original
|
PDF
|
MT54V512H18E
512Kx18)
MT54V512H18E
|
Untitled
Abstract: No abstract text available
Text: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb4 SRAM 9Mb QDR SRAM MT54V512H18E 4-Word Burst FEATURES • 9Mb Density 512Kx18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation
|
Original
|
PDF
|
512Kx18)
MT54V512H18E
|
09005aef809f284b
Abstract: No abstract text available
Text: 288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Features 288Mb CIO Reduced Latency RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9 Features Figure 1: • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization 8 Meg x 36, 16 Meg x 18, and 32 Meg x 9
|
Original
|
PDF
|
288Mb:
288Mb
MT49H8M36
MT49H16M18
MT49H32M9
09005aef80a41b46/Source:
09005aef809f284b
|
MT57W1MH18C
Abstract: MT57W2MH8C MT57W512H36C
Text: ADVANCE‡ 2 MEG x 8, 1 MEG x 18, 512K x 36 1.8V VDD, HSTL, DDR SIO SRAM 18Mb DDR SIO SRAM 2-Word Burst MT57W2MH8C MT57W1MH18C MT57W512H36C FEATURES • 18Mb Density 2 Meg x 8, 1 Meg x 18, 512K x 36 • DLL circuitry for wide-output, data valid window and future frequency scaling
|
Original
|
PDF
|
MT57W2MH8C
MT57W1MH18C
MT57W512H36C
MT57W1MH18C
MT57W2MH8C
MT57W512H36C
|
G38-87
Abstract: MT54W1MH18J MT54W2MH8J MT54W512H36J
Text: ADVANCE‡ 2 MEG x 8, 1 MEG x 18, 512K x 36 1.8V VDD, HSTL, QDRIIb4 SRAM 18Mb QDR II SRAM 4-Word Burst MT54W2MH8J MT54W1MH18J MT54W512H36J FEATURES 165-BALL FBGA • 18Mb Density 2 Meg x 8, 1 Meg x 18, 512K x 36 • DLL circuitry for wide-output, data valid window
|
Original
|
PDF
|
MT54W2MH8J
MT54W1MH18J
MT54W512H36J
165-BALL
MT54W1MH18J
G38-87
MT54W2MH8J
MT54W512H36J
|
Untitled
Abstract: No abstract text available
Text: ADVANCE‡ 2 MEG x 8, 1 MEG x 18, 512K x 36 1.8V VDD, HSTL, DDRIIb4 SRAM 18Mb DDRII CIO SRAM MT57W2MH8J MT57W1MH18J MT57W512H36J 4-Word Burst FEATURES • 18Mb Density 2 Meg x 8, 1 Meg x 18, 512K x 36 • DLL circuitry for wide-output, data valid window
|
Original
|
PDF
|
MT57W1MH18J
|
Untitled
Abstract: No abstract text available
Text: ADVANCE‡ 2 MEG x 8, 1 MEG x 18, 512K x 36 1.8V VDD, HSTL, QDRIIb4 SRAM 18Mb QDR II SRAM 4-Word Burst MT54W2MH8J MT54W1MH18J MT54W512H36J FEATURES 165-BALL FBGA • 18Mb Density 2 Meg x 8, 1 Meg x 18, 512K x 36 • DLL circuitry for wide-output, data valid window
|
Original
|
PDF
|
MT54W1MH18J
|
Untitled
Abstract: No abstract text available
Text: ADVANCE‡ 2 MEG x 8, 1 MEG x 18, 512K x 36 1.8V VDD, HSTL, DDR SIO SRAM 18Mb DDR SIO SRAM 2-Word Burst MT57W2MH8C MT57W1MH18C MT57W512H36C FEATURES • 18Mb Density 2 Meg x 8, 1 Meg x 18, 512K x 36 • DLL circuitry for wide-output, data valid window and future frequency scaling
|
Original
|
PDF
|
MT57W1MH18C
|
micron sram
Abstract: G38-87 MT54W1MH18B MT54W2MH8B MT54W512H36B RESistor 1R
Text: ADVANCE‡ 2 MEG x 8, 1 MEG x 18, 512K x 36 1.8V VDD, HSTL, QDRIIb2 SRAM 18Mb QDR II SRAM 2-Word Burst MT54W2MH8B MT54W1MH18B MT54W512H36B FEATURES 165-BALL FBGA • 18Mb Density 2 Meg x 8, 1 Meg x 18, 512K x 36 • DLL circuitry for wide-output, data valid window
|
Original
|
PDF
|
MT54W2MH8B
MT54W1MH18B
MT54W512H36B
165-BALL
micron sram
G38-87
MT54W1MH18B
MT54W2MH8B
MT54W512H36B
RESistor 1R
|
micron 40h resistor
Abstract: MT8LSDT1664HG-662 marking 8Fh API 662 MT8LSDT864HG-10EB5
Text: 4, 8, 16 MEG X 64 SDRAM SODIMMs SMALL-OUTLINE SDRAM MODULE “ " S ft" " ' For the latest full-length data sheet, please refer to the Micron Web site: www. micron. com/mii/msp/htmi/datasheeL html FEATURES PIN ASSIGNMENT Front View • JEDEC-standard 144-pin, small-outline, dual in-line
|
OCR Scan
|
PDF
|
SMT8LSDT864
144-pin,
128MB
144-PIN
128MB,
6/99a
micron 40h resistor
MT8LSDT1664HG-662
marking 8Fh
API 662
MT8LSDT864HG-10EB5
|