MIPS 32-BIT BUS ARCHITECTURE Search Results

MIPS 32-BIT BUS ARCHITECTURE Result Highlights (5)

Part	Manufacturer	Description
TMPM3HMFYAFG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003
TMPM3HPFYADFG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP128-1420-0.50-001
TMPM3HNFDBFG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP100-1414-0.50-002
TMPM3HLFYAUG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP64-1010-0.50-003
TMPM3HNFZAFG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP100-1414-0.50-002

MIPS 32-BIT BUS ARCHITECTURE Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: V320USC Universal System Controller PCI System Controller for 32-Bit MIPS and SuperH™ System Interface • Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI bus • Programmable chip select / peripheral device	OCR Scan	V320USC 32-Bit	PDF
Untitled Abstract: No abstract text available Text: V320USC Universal System Controller • • • • • • PCI System Controller for 32-Bit MIPS and SuperH™ System Interface Device Highlights Overview • Glueless interface between popular MIPS and SuperH processors and the standard 32-bit PCI bus	Original	V320USC 32-Bit	PDF
Untitled Abstract: No abstract text available Text: V320USC Universal System Controller • • • • • • PCI System Controller for 32-Bit MIPS and SuperH™ System Interface Device Highlights Overview • Glueless interface between popular MIPS and SuperH processors and the standard 32-bit PCI bus	Original	V320USC 32-Bit	PDF
Untitled Abstract: No abstract text available Text: in te i 80960SA/80960SB EMBEDDED 32-BIT PROCESSORS WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 16 MIPS Burst Execution at 16 MHz — 5 MIPS* Sustained Execution at 16 MHz Built-In Interrupt Controller — 4 Direct Interrupt Pins — 32 Priority Levels 256 Vectors	OCR Scan	80960SA/80960SB 32-BIT 16-BIT 80960SB 512-Byte	PDF
AD27 Abstract: AD29 V320USC V320USC-75 AD1485 Text: DS-UC01-0102.fm Page 1 Wednesday, June 30, 1999 7:30 PM Datasheet V320USC Universal System Controller PCI System Controller for 32-Bit MIPS and SuperH™ System Interface • Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI bus	Original	DS-UC01-0102 V320USC 32-Bit DS-UC01-0102 AD27 AD29 V320USC-75 AD1485	PDF
80960SA Abstract: 80960SB 65A176 AD427 Text: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded ■ Pin Compatible with 80960SB Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache	Original	80960SA 32-BIT 16-BIT 80960SB 512-Byte 80960SA 80960SB 65A176 AD427	PDF
Untitled Abstract: No abstract text available Text: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins	OCR Scan	80960SB 32-BIT 16-BIT 512-Byte 16-Bit 8096SA 4fl2bl75	PDF
VAX-11 Abstract: PLCC 68 intel package dimensions 270917 w1a31 intel core i7 processors their registers in term of 32-bit mode Text: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped	OCR Scan	80960SA 32-BIT 16-BIT 512-Byte Local\32-Bit 80960SB 80-Lead VAX-11 PLCC 68 intel package dimensions 270917 w1a31 intel core i7 processors their registers in term of 32-bit mode	PDF
Untitled Abstract: No abstract text available Text: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped	OCR Scan	80960SA 32-BIT 16-BIT 512-Byte 80960SB 16-Bit 80960SA	PDF
T7 DIODE Abstract: No abstract text available Text: inttJ PBßyiiflOMÄlHV 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped	OCR Scan	80960SA 32-BIT 16-BIT 512-Byte 80960KA/ 80960SB T7 DIODE	PDF
QFP PACKAGE thermal resistance Abstract: 80960SA 80960SB N80960SB1 65A176 AD928 Text: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture ■ Built-in Interrupt Controller — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache	Original	80960SB 32-BIT 16-BIT 512-Byte 80960SA 80960SA 80960SB QFP PACKAGE thermal resistance N80960SB1 65A176 AD928	PDF
n80960sb Abstract: No abstract text available Text: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins	OCR Scan	80960SB 32-BIT 16-BIT 512-Byte 16-Bit 8096SA MflEbl75 n80960sb	PDF
QFP PACKAGE thermal resistance Abstract: 65a176 AD427 80960SA 80960SB x80960SB 272207 D010D Text: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture ■ Built-in Interrupt Controller — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache	Original	80960SB 32-BIT 16-BIT 512-Byte 80960SA 80960SA 80960SB QFP PACKAGE thermal resistance 65a176 AD427 x80960SB 272207 D010D	PDF
Untitled Abstract: No abstract text available Text: LOW-COST EMBEDDED ORION RISC MICROPROCESSOR FEATURES • High-performance embedded 64-bit microprocessor - 64-bit integer operations - 64-bit registers - Based on the MIPS RISC Architecture - 80MHz, 100MHz, 133MHz operation frequency - 32-bit bus interface brings 64-bit power to 32-bit sys	OCR Scan	64-bit 80MHz, 100MHz, 133MHz 32-bit 133MHz	PDF

Untitled Abstract: No abstract text available Text: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached	OCR Scan	80960SB 32-BIT 16-BIT 512-Byte 80960SA 32-Blt	PDF
Untitled Abstract: No abstract text available Text: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • ■ ■ High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached	OCR Scan	80960SA 32-BIT 16-BIT 512-Byte 80960SB 80-Lead 84-Le	PDF
Untitled Abstract: No abstract text available Text: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached	OCR Scan	80960SA 32-BIT 16-BIT 512-Byte 32-Blt 80960SB 80-Lead	PDF
80960SA Abstract: 80960SB 65A176 272206-003 Text: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached	Original	80960SA 32-BIT 16-BIT 512-Byte 80960SB 80-Lead 80960SA 80960SB 65A176 272206-003	PDF
VAX-11 Abstract: 272207 Text: in t t J P ß m oM ow A nv 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped	OCR Scan	80960SB 32-BIT 16-BIT 512-Byte 80960KA/ 80960SA 8096SA VAX-11 272207	PDF
V320USC Abstract: No abstract text available Text: V320USC HIGH INTEGRATION, LOW COST PCI SYSTEM CONTROLLER For 32 Bit MIPS and SuperH™ Processors ▼ Glueless interface between the popular MIPS™ and SuperH™ processors and the industry standard PCI Bus ▼ Fully compliant with PCI 2.2 specification	Original	V320USC 32byte V320USC 2348G USC0000	PDF
Am29050 Abstract: No abstract text available Text: FEB 2 0 1991 Advance Information a Am29050 Advanced Micro Devices Streamlined Instruction Microprocessor DISTINCTIVE CHARACTERISTICS • Full 32-bit, three-bus architecture ■ 192 general-purpose registers ■ 32 million instructions per second MIPS sustained at 40 MHz	OCR Scan	Am29050 32-bit, 1024-byte 80-megaflop 64-entry 20-MHz	PDF
5261A Abstract: MIPS 32-bit bus architecture ieee 32 bit floating point multiplier GALILEO TECHNOLOGY 32-bit microprocessor pipeline architecture V340HPC Marvell IEEE754 RM5231A RM5261A Text: RM5231A/5261A 64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus FEATURES • Dual-Issue 64-bit Superscalar architecture • High-performance 64-bit integer unit • High-throughput fully pipelined 64bit floating point unit IEEE754 • High performance SysAD interface	Original	RM5231A/5261A 64-Bit 32/64-Bit 64bit IEEE754) 32-bit 5261A MIPS 32-bit bus architecture ieee 32 bit floating point multiplier GALILEO TECHNOLOGY 32-bit microprocessor pipeline architecture V340HPC Marvell IEEE754 RM5231A RM5261A	PDF
Untitled Abstract: No abstract text available Text: Features • CPU32+ Processor 4.5 MIPS at 25 MHz • • • • • • • • • • • • • • • – 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32) – Background Debug Mode – Byte-misaligned Addressing Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)	Original	CPU32+ 32-bit CPU32 CPU32) TS68040 TSPC603e DC415/D	PDF
SIM60 Abstract: 8a 2113A atmel 748 MC68302 PA15 TS68040 TS68302 TS68EN360 smd marking 58a S43 SMD Text: Features • CPU32+ Processor 4.5 MIPS at 25 MHz • • • • • • • • • • • • • • • – 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32) – Background Debug Mode – Byte-misaligned Addressing Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)	Original	CPU32+ 32-bit CPU32 CPU32) TS68040 TSPC603e DC415/D SIM60 8a 2113A atmel 748 MC68302 PA15 TS68302 TS68EN360 smd marking 58a S43 SMD	PDF

MIPS 32-BIT BUS ARCHITECTURE Search Results

MIPS 32-BIT BUS ARCHITECTURE Result Highlights (5)

MIPS 32-BIT BUS ARCHITECTURE Datasheets Context Search

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AD27

80960SA

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VAX-11

Untitled

T7 DIODE

QFP PACKAGE thermal resistance

n80960sb

QFP PACKAGE thermal resistance

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80960SA

VAX-11

V320USC

Am29050

5261A

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SIM60