MT48LC2M8K3 Search Results

1994 sdram

Abstract: 48LC2M
Text: ADVANCE l^ ic n o N MT48LC2M8K3 S 2 MEG x 8 SDRAM 2 MEG x 8 SDRAM H D A M IJ n * * I V I Level RAS, Single Bank, BURST Mode, 3.3V, SELF REFRESH PIN ASSIGNMENT Top View • Fully synchronous; all signals registered to positive edge of system clock • JEDEC-standard 3.3V power supply