Contextual Info: 4 MEG x 4 EDO DRAM MT4LC4M4E8, MT4LC4M4E9 DRAM For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View • Industry-standard x4 pinout, timing, functions and packages

Contextual Info: PRELIMINARY MT4LC4007J S 1 MEG X 4 DRAM DRAM 1 MEG x 4 DRAM 3.3V EDO PAGE MODE, OPTIONAL SELF REFRESH FEATURES • • • • • • • • • • Single +3.3V ±0.3V power supply Low power, 250|xW standby; lOOmW active, typical JEDEC-standard pinout and packages

Contextual Info: MICRON I MT4LC4M4A1 S 4 MEG X 4 DRAM TECHNOLOGY. INC. DRAM 4 MEG x 4 DRAM 4K REFRESH, 3.3V, FAST PAGE MODE, OPTIONAL SELF REFRESH FEATURES • JEDEC- and industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process

Contextual Info: PRELIMINARY MT4LC4007J S 1 MEG X 4 DRAM I^IICRON 1 MEG x 4 DRAM DRAM FEATURES • • • • • • • • • • PIN ASSIGNMENT (Top View) Single +3.3V ±0.3V power supply Low power, 0.25mW standby; 115mW active, typical JEDEC-standard pinout and packages

Contextual Info: PRELIMINARY M IC R O N ‘ » Eg R>4'n' DRAM MT4LC4M16R6 FEATURES • Single +3.3V +0.3V pow er supply • Industry-standard xl6 pinout, timing, functions and package • 12 row, 10 colum n addresses • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible

4c4m4a

Abstract: Y7A MARKING
Contextual Info: 4 MEG X 4 FPM DRAM I^ IIC R C IN MT4LC4M4B1,MT4C4M4B1 MT4LC4M4A1,MT4C4M4A1 n R AM ^ r » »1 FEATURES • Industry-standard x4 pinout, timing, functions and packages • State-of-the-art, high-performance, low power CMOS silicon-gate process • Single power supply +3.3V ±0.3V or +5V ±10%

MT4LC400

Contextual Info: MT4LC4001 J S 1 MEG X 4 DRAM M IC R O N DRAM 1 MEG x 4 DRAM 3.3V, FAST PAGE MODE OPTIONAL SELF REFRESH PIN ASSIGNMENT (Top View) • Single +3.3V ±0.3V power supply • Low power, 0.3m W standby; lOOmW active, typical • Industry-standard x4 pinout, tim ing, functions and

MT4LC4M16R6

Abstract: MT4LC4M16R6TG5 MT4LC4M16R6TG-5
Contextual Info: PRELIMINARY 4 MEG x 16 EDO DRAM TECHNOLOGY, INC. MT4LC4M16R6 DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x16 pinout, timing, functions and package • 12 row, 10 column addresses • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible

Contextual Info: MT4LC4M4E8 L 4 MEG x 4 DRAM TECHNOLOGY, INC. DRAM 4 MEG x 4 DRAM 3.3V, EDO PAGE MODE, OPTIONAL EXTENDED REFRESH FEATURES PIN ASSIGNMENT (Top View) • Industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process

LN 9297

Contextual Info: D24A 16 MEG DRAM DIE I ^ I C R O N DRAM DIE 16 MEG DRAM MT4LC4M4B1D24A, MT4LC4M4E8D24A, MT4LC1M16C3D24A, MT4LC1M16E5D24A FEATURES DIE DATA BASE D24A DIE OUTLINE see page 4 • S in g le 3 .3 V (x4, x l 6 ) p o w e r su p p ly • In d u stry -s ta n d a rd x4, x l 6 tim in g an d fu n c tio n s

Contextual Info: MT4LC4M4B1 S 4 MEG X 4 DRAM MICRON • TECHNOLOGY, MC. DRAM 4 MEG x 4 DRAM 2K REFRESH, 3.3V, FAST PAGE MODE, OPTIONAL SELF REFRESH FEATURES • JEDEC- and industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process

Contextual Info: DRAM MT4LC4M16F5 For the latest full-length data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/ datasheet.html FEATURES • Single +3.3V +0.3V pow er sup p ly • Industry-standard x l6 pinout, timing, functions and packages • 12 row, 10 colum n addresses

Contextual Info: MT4LC4M4B1 L 4 MEG X 4 DRAM MICRON 4 MEG x 4 DRAM DRAM 3.3V, FAST PAGE MODE, OPTIONAL EXTENDED REFRESH FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access -6 -7 • Packages Plastic SOJ (300 mil) DJ • Refresh Rate Standard 32ms period

Contextual Info: ADVANCE MT4LC4M16N3/R6 4 MEG X 16 DRAM l^ iic n g N 4 M E G X 16 D R A M S DRAM 3.3V, EDO PAGE MODE PIN ASSIGNMENT Top View • Single +3.3V +0.3V power supply • Industry-standard x l6 pinout, timing, functions and package • 13 row-addresses, 9 column-addresses (N3) or

Contextual Info: M IC R O N I .PPM DRAM 4 MEG X 16 MT4LC4M16F5 DRAM For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES • Single +3.3V +0.3V power supply • Industry-standard x l6 pinout, timing, functions and

Contextual Info: 4 MEG x 4 EDO DRAM MICRON TECHNOLOGY. INC. lì R A M L S r T M IV I MT4LC4M4E8, MT4C4M4E8 MT4LC4M4E9, MT4C4M4E9 FEATURES PIN ASSIGNMENT Top View • Industry-standard x4 pinout, timing, functions and packages • State-of-the-art high-performance, low power CMOS

Contextual Info: MICRON 4M E Gx4 . FPM DRAM DRAM MT4LC4M4B1, MT4LC4M4A1 For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html

Contextual Info: MICRON' I 4 MEG x 16 E D O D R A lV l TECHNOLOGY, INC. n P A M MT4LC4M16R6 MT4LC4M16N3 U r iM IV I For the latest data sheet, please refer to the Micron Web site: www. micron, com/mti/msp/html/datasheet. html FEATURES PIN ASSIGNMENT Top View • Single +3.3V +0.3V power supply

mt4lc4m16r6

Contextual Info: PRELIMINARY 4 M E G x 16 EDO DRAM I^ IIC R D N MT4LC4M16R6 DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x l6 pinout, timing, functions and package • 12 row, 10 column addresses • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible

mt4lc4m4e8dj-6

Contextual Info: 4 MEG x 4 EDO DRAM V U C Z R O N D R A M L /n # 4 IV I MT4LC4M4E8, MT4C4M4E8 MT4LC4M4E9, MT4C4M4E9 FEATURES PIN ASSIGNMENT (Top View OPTIONS 24/26-Pin SOJ (DA-2) V cc q 1 • DQ1 [ 2 DQ2 d 3 WE# : 4 RAS# : 5 NC/A11 c 6 A10 A0 A1 A2 A3 V cc c q : L q [ B

MT4C4M4A1TG-6S

Abstract: MT4LC4M4B1TG-6S
Contextual Info: 4 MEG x 4 FPM DRAM MT4LC4M4B1, MT4C4M4B1 MT4LC4M4A1, MT4C4M4A1 DRAM For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View • Industry-standard x4 pinout, timing, functions,

M995

Contextual Info: |V |IC Z R O N MT4LC4M4B1 L 4 MEG X 4 DRAM DRAM 4 MEG x 4 DRAM 3.3V, FAST PAGE MODE, OPTIONAL EXTENDED REFRESH FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access -6 -7 • Packages Plastic SOJ (300 mil) DJ • Refresh Rate

Contextual Info: M IC R O N D24A 16 MEG DRAM DIE I DRAM DIE 16 MEG DRAM MT4C4M4B1D24A, MT4LC4M4B1D24A MT4LC2M8B1D24A, MT4LC1M16C3D24A FEATURES DIE OUTLINE Top View • • • • • • Single 5.0V (x4 only) or 3.3V (x4, x8, x l6) pow er supply Industry-standard x4, x8, x l6 timing and functions

Contextual Info: 4O M E Gx4 E D D R A M MICRON I .'.JLT n R A M U n A lv i MT4LC4M4E8, MT4C4M4E8 MT4LC4M4E9, MT4C4M4E9 FEATURES * * * * * * * * * PIN A S S I G N M E N T Top View Industry-standard x4 pinout, timing, functions and packages State-of-the-art high-performance, low power CMOS