N24E
Abstract: No abstract text available
Text: 24 Lead 0 400 Wide Molded Dual-in-Line Package NS Package Number N24E All dimensions are in inches (millimeters) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
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100314
Abstract: 100314PC 100314QC 100314QI 100314SC F100K M24B MO-047 MS-013 N24E
Text: Revised August 2000 100314 Low Power Quint Differential Line Receiver General Description Features The 100314 is a monolithic quint differential line receiver with emitter-follower outputs. An internal reference supply VBB is available for single-ended reception. When used in
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F100K
100314
100314PC
100314QC
100314QI
100314SC
F100K
M24B
MO-047
MS-013
N24E
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100302PC
Abstract: 100302QC 100302QI 100302SC M24B MO-047 MS-013 N24E V28A
Text: Revised August 2000 100302 Low Power Quint 2-Input OR/NOR Gate General Description Features The 100302 is a monolithic quint 2-input OR/NOR gate with common enable. All inputs have 50 kΩ pull-down resistors and all outputs are buffered. • 43% power reduction of the 100102
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100302SC
24-Lead
MS-013,
100302PC
MS-010,
10030WITHOUT
100302PC
100302QC
100302QI
100302SC
M24B
MO-047
MS-013
N24E
V28A
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100325PC
Abstract: F100K M24B MO-047 MS-013 N24E V28A 100325QC 100325QI 100325SC
Text: Revised August 2000 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential
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F100K
100325PC
M24B
MO-047
MS-013
N24E
V28A
100325QC
100325QI
100325SC
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100353PC
Abstract: 100353QC 100353QI MO-047 N24E V28A
Text: Revised August 2000 100353 Low Power 8-Bit Register General Description Features The 100353 contains eight D-type edge triggered, master/ slave flip-flops with individual inputs Dn , true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN).
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100323PC
Abstract: 100323QC F100K MO-047 N24E V28A
Text: Revised August 2000 100323 Low Power Hex Bus Driver General Description Features The 100323 is a monolithic device containing six bus drivers capable of driving terminated lines with terminations as low as 25Ω. To reduce crosstalk, each output has its own
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F100K
100323PC
100323QC
MO-047
N24E
V28A
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Untitled
Abstract: No abstract text available
Text: Revised November 1999 100323 Low Power Hex Bus Driver General Description Features The 100323 is a monolithic device containing six bus drivers capable of driving terminated lines with terminations as low as 25Ω. To reduce crosstalk, each output has its own
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F100K
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DS009879
Abstract: No abstract text available
Text: Revised November 1999 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential
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F100K
DS009879
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B7S2
Abstract: multiplexer 100363 100363PC 100363QC 100363QI MO-047 MS-011 N24E V28A
Text: Revised November 1999 100363 Low Power Dual 8-Input Multiplexer General Description Features The 100363 is a dual 8-input multiplexer. The Data Select Sn inputs determine which bit (An and Bn) will be presented at the outputs (Za and Zb respectively). The same
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100363PC
24-Lead
MS-011,
B7S2
multiplexer 100363
100363PC
100363QC
100363QI
MO-047
MS-011
N24E
V28A
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F100K
Abstract: No abstract text available
Text: 100321 Low Power 9-Bit Inverter General Description The 100321 is a monolithic 9-bit inverter. The device contains nine inverting buffer gates with single input and output. All inputs have 50 kΩ pull-down resistors. n n n n n 2000V ESD protection Pin/function compatible with 100121
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MIL-STD-883
DS010609-1
DS010609
F100K
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F100K
Abstract: No abstract text available
Text: 100331 Low Power Triple D Flip-Flop General Description Features The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock CPC , and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct
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100329PC
Abstract: 100329QC 100329QI MO-047 N24E V28A
Text: Revised August 2000 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register General Description Features The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determined by the DIR input. A LOW on the output enable input
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100354PC
Abstract: 100354QC 100354QI MO-047 N24E V28A
Text: Revised August 2000 100354 Low Power 8-Bit Register with Cut-Off Drivers General Description The 100354 contains eight D-type edge triggered, master/ slave flip-flops with individual inputs Dn , true outputs (Qn), a clock input (CP), an output enable pin (OEN), and a common clock enable pin (CEN). Data enters the master when
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100391PC
Abstract: 100391QC 100391QI 100391SC F100K M24B MO-047 MS-013 N24E V28A
Text: Revised August 2000 100391 Low Power Single Supply Hex TTL-to-PECL Translator General Description Features The 100391 is a hex translator for converting TTL logic levels to F100K PECL logic levels. The unique feature of this translator, is the ability to do this translation using only one
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F100K
100391PC
100391QC
100391QI
100391SC
M24B
MO-047
MS-013
N24E
V28A
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Untitled
Abstract: No abstract text available
Text: Revised August 2000 100351 Low Power Hex D-Type Flip-Flop General Description Features The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs CPa and CPb and common Master Reset (MR) input. Data enters a master when both CPa
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b1565
Abstract: B1565 transistor 870b 24-Pin Plastic DIP B955 transistor b1565 C1995 F100K J24E N24E
Text: 100304 Low Power Quint AND NAND Gate General Description Features The 100304 is monolithic quint AND NAND gate The Function output is the wire-NOR of all five AND gate outputs All inputs have 50 kX pull-down resistors Y Y Y Y Y Y Logic Symbol Low Power Operation
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MIL-STD-883
24-Pin
b1565
B1565 transistor
870b
24-Pin Plastic DIP
B955
transistor b1565
C1995
F100K
J24E
N24E
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b37 diode
Abstract: C1995 F100K J24E M24B N24E V28A W24B 1380B
Text: 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels Differential inputs allow each circuit to be used as an inverting non-inverting or differential receiver An internal reference voltage generator provides
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F100K
b37 diode
C1995
J24E
M24B
N24E
V28A
W24B
1380B
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Untitled
Abstract: No abstract text available
Text: Se mi c o n dut July 1992 t o r 100331 Low Power Triple D Flip-Flop General Description Features The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Com mon Clock CPc , and Master Set (MS) and Master Reset
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Untitled
Abstract: No abstract text available
Text: A I R C H I I - D EMIC O N D U C T O R T 100351 Low Power Hex D Flip-Flop General Description Features The • 4 0 % p o w e r re d u c tio n o f th e 100151 100351 c o n ta in s s ix D -ty p e e d g e -trig g e re d , m a s te r/ s la v e flip -flo p s w ith tru e a n d c o m p le m e n t o u tp u ts , a p a ir o f
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Untitled
Abstract: No abstract text available
Text: S E M IC O N D U C T O R tm 100354 Low Power 8-Bit Register with Cut-Off Drivers General Description The 100354 contains eight D-Type edge triggered, master/ slave flip-flops with individual inputs Dn , true outputs (Qn), a clock input (CP), an output enable pin (OEN), and a com
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Untitled
Abstract: No abstract text available
Text: S E M IC O N D U C T O R T M 100302 Low Power Quint 2-Input OR/NOR Gate General Description • 2000V ESD protection The 100302 is a m onolithic quint 2 -input O R /N O R gate with com m on enable. All inputs have 50 kQ pull-dow n resistors and all outputs are buffered.
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Untitled
Abstract: No abstract text available
Text: S E M IC O N D U C T O R tm 100322 Low Power 9-Bit Buffer General Description • 2000V ESD protection The 100322 is a m onolithic 9-bit buffer. The device contains nine non-inverting buffer gates w ith single input and output. All inputs have 50 kQ pull-down resistors and all outputs are
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Untitled
Abstract: No abstract text available
Text: S E M IC O N D U C T O R tm 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex tra n sla tor fo r converting F100K logic levels to T T L logic levels. D ifferential inputs allo w each circuit to be used as an inverting, non-inverting or differential re
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F100K
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Untitled
Abstract: No abstract text available
Text: S E M IC O N D U C T O R - r. 100398 Quad Differential ECL/TTL Translating Transceiver with Latch General Description to turn off w hen the high im pedance to duces term ination noise m argin w hen The 100398 is a quad latched tra n sce ive r designed to c o n
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F100K
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