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    PORT INTERCONNECT Search Results

    PORT INTERCONNECT Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    FO-62.5LPBMT0-001 Amphenol Cables on Demand Amphenol FO-62.5LPBMT0-001 MT-RJ Connector Loopback Cable: Multimode 62.5/125 Fiber Optic Port Testing .1m Datasheet
    FO-9LPBMTRJ00-001 Amphenol Cables on Demand Amphenol FO-9LPBMTRJ00-001 MT-RJ Connector Loopback Cable: Single-Mode 9/125 Fiber Optic Port Testing .1m Datasheet
    SF-SFP28LPB1W-3DB Amphenol Cables on Demand Amphenol SF-SFP28LPB1W-3DB SFP28 Loopback Adapter Module for SFP28 Port Compliance Testing - 3dB Attenuation & 1W Power Consumption Datasheet
    FO-50LPBMTRJ0-001 Amphenol Cables on Demand Amphenol FO-50LPBMTRJ0-001 MT-RJ Connector Loopback Cable: Multimode 50/125 Fiber Optic Port Testing .1m Datasheet
    SF-SFPPLOOPBK-003.5 Amphenol Cables on Demand Amphenol SF-SFPPLOOPBK-003.5 SFP+ Loopback Adapter Module for SFP+ Port Compliance Testing - 3.5dB Copper/Optical Cable Emulation Datasheet

    PORT INTERCONNECT Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    AL010

    Abstract: AR11 AR12 CY7C132 CY7C142 DR31 "Single-Port RAM"
    Text: Understanding Asynchronous Dual-Port RAMs This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress’s asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in


    Original     		PDF Comm1997. AL010 AR11 AR12 CY7C132 CY7C142 DR31 "Single-Port RAM"

    dual port ram

    Abstract: AR11 AR12 CY7C132 CY7C142 DR31
    Text: Understanding Asynchronous Dual-Port RAMs This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress’s asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in


    Original     		PDF

    BC634

    Abstract: AA012 DSP56800 bc645 BC699 bc657
    Text: SECTION 12 JTAG PORT DSP56L811 User’s Manual 12-1 JTAG Port 12.1 12.2 12.3 12.4 12.5 12-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 JTAG PORT ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . 12-4 JTAG/ONCE PORT PINOUT. . . . . . . . . . . . . . . . . . . . . . . . 12-5


    Original     		PDF DSP56L811 BC634 AA012 DSP56800 bc645 BC699 bc657

    CYPRESS CROSS REFERENCE dual port sram

    Abstract: 1024 byte dual port memory "8-Bit Microprocessors" CY7C132 dual port sram dual port SRAM PLCC dual-port RAM AR11 AR12 CY7C142
    Text: fax id: 5300 Understanding Asynchronous Dual-Port RAMs This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress’s asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: 16-Lane 16-Port PCIe Gen2 System Interconnect Switch 89HPES16NT16G2 Datasheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions


    Original     		PDF 16-Lane 16-Port 89HPES16NT16G2 32/64-bit

    Untitled

    Abstract: No abstract text available
    Text: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24BG2 Datasheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions


    Original     		PDF 32-Lane 24-Port 89HPES32NT24BG2 32/64-bit

    Untitled

    Abstract: No abstract text available
    Text: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24AG2 Datasheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions


    Original     		PDF 32-Lane 24-Port 89HPES32NT24AG2 32/64-bit

    XRS10L240

    Abstract: sor1 redundant transmission signal path designer
    Text: PRELIMINARY XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR MARCH 2006 REV. P1.0.1 INTRODUCTION The XRS10L240 device provides the combined advantages of the Serial ATA II Port Selector and Port Multiplier implementations for Serial ATA II systems


    Original     		PDF XRS10L240 XRS10L240 sor1 redundant transmission signal path designer

    Untitled

    Abstract: No abstract text available
    Text: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24AG2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions


    Original     		PDF 32-Lane 24-Port 89HPES32NT24AG2 32/64-bit

    89H16NT16G2

    Abstract: 89HPES16NT16G2
    Text: 16-Lane 16-Port PCIe Gen2 System Interconnect Switch 89HPES16NT16G2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions


    Original     		PDF 16-Lane 16-Port 89HPES16NT16G2 PES16NT16G2 16-lane, 89H16NT16G2

    PM3370

    Abstract: PM3380 PM3390
    Text: /D\HUDQG*LJDELW WKHUQHW6ZLWFKLQJ 6ROXWLRQV EXACT Port Controller (PM3380, PM3370 EXACT Port Controller (PM3380, PM3370) EXACT Port Controller (PM3380, PM3370) EXACT Port Controller (PM3380, PM3370) Optional EXACT Switch Matrix Controller (PM3390)


    Original     		PDF PM3380, PM3370) PM3390) PM3370 PM3380 PM3390

    port expander 32-bit i2c

    Abstract: 89HPES32NT24BG2 89H32NT24BG2
    Text: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24BG2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions


    Original     		PDF 32-Lane 24-Port 89HPES32NT24BG2 PES32NT24BG2 32-lane, 24port port expander 32-bit i2c 89H32NT24BG2

    PES32NT24AG2

    Abstract: 89H32NT24A 89H32NT24 89H32NT24AG2 89HPES32NT24AG2
    Text: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24AG2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions


    Original     		PDF 32-Lane 24-Port 89HPES32NT24AG2 PES32NT24AG2 32-lane, 24port 89H32NT24A 89H32NT24 89H32NT24AG2

    PES16NT16G2

    Abstract: 89H16NT16G2
    Text: 16-Lane 16-Port PCIe Gen2 System Interconnect Switch 89HPES16NT16G2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions


    Original     		PDF 16-Lane 16-Port 89HPES16NT16G2 PES16NT16G2 16-lane, 89H16NT16G2

    89HPES16NT16G2

    Abstract: 89hpes16nt16g2 port interconnect 89H16NT16 89H16NT16G2
    Text: 16-Lane 16-Port PCIe Gen2 System Interconnect Switch 89HPES16NT16G2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions


    Original     		PDF 16-Lane 16-Port 89HPES16NT16G2 PES16NT16G2 16-lane, 89hpes16nt16g2 port interconnect 89H16NT16 89H16NT16G2

    Untitled

    Abstract: No abstract text available
    Text: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24BG2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions


    Original     		PDF 32-Lane 24-Port 89HPES32NT24BG2 32/64-bit

    simple switch block diagram

    Abstract: PM3370 PM3380 PM3390
    Text: PM3380 Preliminary Information PM3380 Gigabit Switch Port Controller FEATURES VLAN EXACT INTERWORKING • Monolithic intelligent Gigabit Ethernet Switch Port Controller. • Allows up to 32 Port or MAC based VLANs. • Interworks with the PM3370 Octal 10/100 Switch Port Controller.


    Original     		PDF PM3380 PM3380 PM3370 PM3390 PM3390 PMC-980236 simple switch block diagram

    Untitled

    Abstract: No abstract text available
    Text: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24AG2 Data Sheet ® Devic e Ove r vie w • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions


    Original     		PDF 32-Lane 24-Port 89HPES32NT24AG2 32/64-bit

    XRS10L240

    Abstract: MDIO 000D MDIO clause 45 specification
    Text: PRELIMINARY & CONFIDENTIAL EXTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR JUNE 2006 1.0 REV. P1.0.2 INTRODUCTION The XRS10L240 provides the combined advantages of the Serial ATA II Port Selector and Port Multiplier implementations for Serial ATA II systems at 3.0


    Original     		PDF XRS10L240 XRS10L240 MDIO 000D MDIO clause 45 specification

    Untitled

    Abstract: No abstract text available
    Text: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24BG2 Data Sheet ® Devic e Ove r vie w • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions


    Original     		PDF 32-Lane 24-Port 89HPES32NT24BG2 32/64-bit

    ECP88

    Abstract: No abstract text available
    Text: PARALLEL PORT The FDC37C669 incorporates an IBM XT/AT compatible parallel port. The FDC37C669 supports the optional PS/2 type bi­ directional parallel port SPP , the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the


    OCR Scan     		PDF FDC37C669 ECP88

    M1012L

    Abstract: 7 segmen CASE DIODE A5L
    Text: QS7025A PRELIMINARY Q High-Speed CMOS 8K x 16 Asynchronous Dual-Port RAM FEATURES QS7025A DESCRIPTION High-speed asynchronous dual-port architecture Access times from either port, 20/25/35/55 ns Industry standard pin-out Independent port access and control


    OCR Scan     		PDF QS7025A QS7025A 100-pin 84-pin 128K-bit 32-bit -40PC M1012L 7 segmen CASE DIODE A5L

    Signal Path Designer

    Abstract: No abstract text available
    Text: jy&cm RF Hybrid Devices Overview its difference port. Opposite ports of the hybrid are isolated. Figure 1 is a functional diagram which will be used in this article to represent the 180° hybrid. Port B can be considered the sum port with port A the difference port. Ports A and B and ports


    OCR Scan     		PDF

    7 segmen

    Abstract: 11DDDD
    Text: QS7025A PRELIMINARY High-Speed CMOS 8K x 16 Asynchronous Dual-Port RAM Q FEATURES QS7025A DESCRIPTION High-speed asynchronous dual-port architecture Access times from either port, 20/25/35/55 ns Industry standard pin-out Independent port access and control


    OCR Scan     		PDF QS7025A QS7025A 100-pin 84-pin 128K-bit 32-bit -40PC 7 segmen 11DDDD