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    CY7C132 Price and Stock

    Flip Electronics CY7C1321KV18-250BZC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1321KV18-250BZC Tray 1,848 30
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    Flip Electronics CY7C1321KV18-250BZXC

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1321KV18-250BZXC Tray 1,819 30
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    Flip Electronics CY7C1325S-100AXC

    IC SRAM 4.5MBIT PARALLEL 100TQFP
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    DigiKey CY7C1325S-100AXC Tray 1,659 200
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    Flip Electronics CY7C1320KV18-333BZXC

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1320KV18-333BZXC Tray 1,319 25
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    Cypress Semiconductor CY7C1329H-133AXC

    NO WARRANTY
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    DigiKey CY7C1329H-133AXC Tray 489 1
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    Newark CY7C1329H-133AXC Bulk 144
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    CY7C132 Datasheets (395)

    Part ECAD Model Manufacturer Description Curated Type PDF
    CY7C132 Cypress Semiconductor 2Kx8 Dual-Port Static RAM Original PDF
    CY7C132 Unknown 2Kx8 Dual-Port Static RAM Original PDF
    CY7C13201KV18-300BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 300MHZ 165FBGA Original PDF
    CY7C13201KV18-333BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 333MHZ 165FBGA Original PDF
    CY7C1320AV18 Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1320AV18-167BZC Cypress Semiconductor Memory : Sync SRAMs Original PDF
    CY7C1320AV18-200BZC Cypress Semiconductor Memory : Sync SRAMs Original PDF
    CY7C1320AV18-250BZC Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1320BV18 Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1320BV18-167BZC Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1320BV18-167BZC Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1320BV18-167BZCT Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1320BV18-167BZXC Cypress Semiconductor 18-Mbit DDR-II S Original PDF
    CY7C1320BV18-200BZC Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1320BV18-200BZC Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1320BV18-250BZC Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V Original PDF
    CY7C1320BV18-250BZC Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1320BV18-250BZI Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1320CV18 Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1320CV18-167BZC Cypress Semiconductor 18-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    ...

    CY7C132 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    64KX32

    Abstract: 7C13 CY7C1329
    Text: fax id: 1080 1CY 7C13 29 CY7C1329 PRELIMINARY 64K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1329 is 3.3V 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary


    Original     		PDF CY7C1329 CY7C1329 100-MHz 64KX32 7C13

    Untitled

    Abstract: No abstract text available
    Text: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth


    Original     		PDF CY7C1319KV18/CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz CY7C1321KV18

    CY7C1325G

    Abstract: CY7C1325G-133AXC CY7C1325G-133AXI CY7C1325G-133BGC CY7C1325G-133BGI CY7C1325G-133BGXC CY7C1325G-133BGXI
    Text: CY7C1325G PRELIMINARY 4-Mbit 256K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 256K X 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version)


    Original     		PDF CY7C1325G 133-MHz 117-MHz 100-MHz 100-pin 119-ball CY7C1325G CY7C1325G-133AXC CY7C1325G-133AXI CY7C1325G-133BGC CY7C1325G-133BGI CY7C1325G-133BGXC CY7C1325G-133BGXI

    CY7C1327B

    Abstract: No abstract text available
    Text: 327 CY7C1327B 256K x 18 Synchronous-Pipelined Cache RAM Features The CY7C1327B I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states


    Original     		PDF CY7C1327B CY7C1327B 100-MHz 166-MHz 166-Mpress

    CY7C1327G

    Abstract: CY7C1327G-250AXC CY7C1327G-250AXI CY7C1327G-250BGC CY7C1327G-250BGI CY7C1327G-250BGXC CY7C1327G-250BGXI
    Text: CY7C1327G PRELIMINARY 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times


    Original     		PDF CY7C1327G 250-MHz 225-MHz 200-MHz CY7C1327G CY7C1327G-250AXC CY7C1327G-250AXI CY7C1327G-250BGC CY7C1327G-250BGI CY7C1327G-250BGXC CY7C1327G-250BGXI

    7N19

    Abstract: CY7C1316AV18 CY7C1318AV18 CY7C1320AV18
    Text: CY7C1316AV18 CY7C1318AV18 CY7C1320AV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mb density 2M x 8, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at


    Original     		PDF CY7C1316AV18 CY7C1318AV18 CY7C1320AV18 18-Mbit 18-Mb 250-MHz CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 7N19 CY7C1316AV18 CY7C1318AV18 CY7C1320AV18

    CY7C1316BV18

    Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18
    Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 PRELIMINARY 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency


    Original     		PDF CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit 250-MHz CY7C1316BV18 CY7C1318BV18 CY7C1320BV18 CY7C1916BV18

    A101

    Abstract: CY7C1329G CY7C1329G-133AC CY7C1329G-166AC
    Text: CY7C1329G 2-Mb 64K x 32 Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V I/O operation • Fast clock-to-output times counter for internal burst operation. All synchronous inputs are


    Original     		PDF CY7C1329G CY7C1329G -166AC A101 CY7C1329G-133AC CY7C1329G-166AC

    CY7C132

    Abstract: CY7C136 CY7C146
    Text: CY7C132/CY7C136 CY7C142/CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports


    Original     		PDF CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/CY7C136/CY7C142 CY7C146 CY7C132/ CY7C136 16-bit CY7C132

    CY7C1328A

    Abstract: GVT71256F18
    Text: 327 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 128K x 36/256K x 18 Synchronous-Pipelined Cache RAM Features • • • • • • • • • • • • • • • • • Fast access times: 3.5, 3.8, and 4.0 ns Fast clock speed: 166, 150, 133, and 117 MHz


    Original     		PDF CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 36/256K CY7C1328A/GVT71256F18, CY7C1348A/GVT71128F36 CY7C1328A GVT71256F18

    CY7C136-55NI

    Abstract: cy7c136 CY7C132 CY7C142 CY7C146 CY7C146-15NC CY7C136-25JXC CY7C136-55NC
    Text: CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells that enable simultaneous reads of the same memory location ■ 2K x 8 organization ■ 0.65 micron CMOS for optimum speed and power


    Original     		PDF CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 CY7C136, CY7C136-55NI cy7c136 CY7C132 CY7C142 CY7C146 CY7C146-15NC CY7C136-25JXC CY7C136-55NC

    CY7C1328G-200AXC

    Abstract: CY7C1328G CY7C1328G-133AXC CY7C1328G-133AXI CY7C1328G-166AXC
    Text: CY7C1328G 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18 common I/O architecture


    Original     		PDF CY7C1328G 250-MHz 100-Pin 133-MHz CY7C1328G-200AXC CY7C1328G CY7C1328G-133AXC CY7C1328G-133AXI CY7C1328G-166AXC

    CY7C1328G

    Abstract: CY7C1328G-166AXC CY7C1328G-200AXC CY7C1328G-250AXC
    Text: CY7C1328G PRELIMINARY 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18-bit common I/O architecture


    Original     		PDF CY7C1328G 18-bit 250-MHz CY7C1328G CY7C1328G-166AXC CY7C1328G-200AXC CY7C1328G-250AXC

    CY7C1326H

    Abstract: No abstract text available
    Text: CY7C1326H 2-Mbit 128K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 128K x 18 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times


    Original     		PDF CY7C1326H 166-MHz 133-MHz 100-pin CY7C1326H

    intel 8082

    Abstract: intel 80.82 INTEL 80,82
    Text: PRELIMINARY CY7C1325B 256K x 18 Synchronous 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 256K by 18 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wrap-around counter supporting either interleaved or linear burst sequence


    Original     		PDF CY7C1325B 117-MHz 100-pin CY7C1325B intel 8082 intel 80.82 INTEL 80,82

    Untitled

    Abstract: No abstract text available
    Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency


    Original     		PDF CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit 300-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1328G PRELIMINARY 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18-bit common I/O architecture


    Original     		PDF CY7C1328G 18-bit 250-MHz 200-MHz 166-MHz 133-MHz CY7C1328G

    Untitled

    Abstract: No abstract text available
    Text: CY7C1317V18 CY7C1319V18 CY7C1321V18 PRELIMINARY 18-Mb DDR -II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mb density 2M x 8, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency


    Original     		PDF CY7C1317V18 CY7C1319V18 CY7C1321V18 18-Mb 250-MHz p19V18/CY7C1321V18 BB165D BB165A

    Untitled

    Abstract: No abstract text available
    Text: CY7C1324H 2-Mbit 128K x 18 Flow-Through Sync SRAM Features • 128K x 18 common I/O • 3.3V core power supply • 3.3V/2.5V I/O supply • Fast clock-to-output times — 6.5 ns (133-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting Intel


    Original     		PDF CY7C1324H 133-MHz 100-pin

    INTEL 80,82

    Abstract: intel 80.82 intel 8082 INTEL 80-82 CY7C1325 ASYNCHRONOUS COUNTER
    Text: CYPRESS CY7C1325 256K x 18 Synchronous 3.3V Cache RAM Features Functional Description • Supports 117-M Hz microprocessor cache systems with zero wait states • 256K by 18 common I/O • Fast ciock-to-output times — 7.5 ns 117-M Hz version • Two-bit wrap-around counter supporting either inter­


    OCR Scan     		PDF 117-MHz 100-pin CY7C1325 CY7C1325 INTEL 80,82 intel 80.82 intel 8082 INTEL 80-82 ASYNCHRONOUS COUNTER

    Untitled

    Abstract: No abstract text available
    Text: fax id: 5201 CY7C132/CY7C136 CY7C142/CY7C146 W CYPRESS 2Kx8 Dual-Port Static RAM Features Functional Description True Dual-Ported memory cells which allow sim ulta­ neous reads of the same mem ory location 2K x 8 organization 0.65-micron CMOS for optimum speed/power


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 65-micron CY7C132/CY7C136 CY7C132/CY7C136; 52-pin 48-pin CY7C132/142)

    Untitled

    Abstract: No abstract text available
    Text: CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM Features Functional Description • 0.8-raicron CMOS for optimum speed/power • BÜSŸ output flag on CY7C132/ CY7C136; BUSY input on CY7C142/CY7C146 The CY7C132/CY 7C136/CY7C142/


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/ CY7C136; CY7C132/CY 7C136/CY7C142/ 7C146 7C136

    Untitled

    Abstract: No abstract text available
    Text: CY7C1327 256K X 18 Synchronous-Pipelined Cache RAM Features The CY7C1327 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when V DDQ=2.5V. • Supports 1 0O-MHz bus for Pentium and PowerPC operations with zero wait states


    OCR Scan     		PDF CY7C1327 166-MHz 133-MHz 100-MHz CY7C1327

    Z1213

    Abstract: CY7C132 CY7C136 CY7C146 zl12
    Text: bSE » CYPRESS SEMICONDUCTOR SSÖ'lbbE 0 0 0 ^ 7 4 7 ISb I CYP CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM output enable OE . BUSY flags are pro­ vided on each port. In addition, an interrupt Functional Description Features


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 CY7C142/CY7C146 CY7C132/ CY7C136; 52-pin CY7C132/CY7C136/CY7C142/ CY7C146 Z1213 CY7C132 CY7C136 zl12