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    7C136 Price and Stock

    Rochester Electronics LLC CY7C1360A-150ACT

    IC SRAM 9MBIT PAR 150MHZ 100TQFP
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    DigiKey CY7C1360A-150ACT Bulk 750 45
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    Cypress Semiconductor CY7C1361C-100AXE

    NO WARRANTY
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    DigiKey CY7C1361C-100AXE Tray 679 1
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    Flip Electronics CY7C1361C-100AXE 16,103
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    Infineon Technologies AG CY7C1360C-166AXI

    IC SRAM 9MBIT PARALLEL 100TQFP
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    DigiKey CY7C1360C-166AXI Tray 366 1
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    Mouser Electronics CY7C1360C-166AXI 334
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    Chip1Stop CY7C1360C-166AXI Tray 10
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    Infineon Technologies AG CY7C1360C-200AXC

    IC SRAM 9MBIT PARALLEL 100TQFP
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    DigiKey CY7C1360C-200AXC Tray 358 1
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    Mouser Electronics CY7C1360C-200AXC 69
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    Rochester Electronics LLC CY7C136-30JC

    IC SRAM 16KBIT PARALLEL 52PLCC
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    DigiKey CY7C136-30JC Bulk 331 18
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    7C136 Datasheets (6)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    7C136-15 Cypress Semiconductor 2Kx8 Dual-Port Static RAM Original PDF
    7C136-25 Cypress Semiconductor 2Kx8 Dual-Port Static RAM Original PDF
    7C136-30 Cypress Semiconductor 2Kx8 Dual-Port Static RAM Original PDF
    7C136-35 Cypress Semiconductor 2Kx8 Dual-Port Static RAM Original PDF
    7C136-45 Cypress Semiconductor 2Kx8 Dual-Port Static RAM Original PDF
    7C136-55 Cypress Semiconductor 2Kx8 Dual-Port Static RAM Original PDF

    7C136 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: 7C1361A 7C1363A 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0ns Fast clock speed: 150, 133, 117, and 100MHz Fast OE access times: 3.5 ns and 4.0 ns


    Original     		PDF CY7C1361A CY7C1363A 36/512K 100MHz CY7C1361A/CY7C1363A

    CY7C132

    Abstract: CY7C136 CY7C146
    Text: CY7C132/7C136 CY7C142/CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location The CY7C132/7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports


    Original     		PDF CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/CY7C136/CY7C142 CY7C146 CY7C132/ CY7C136 16-bit CY7C132

    CY7C1362A

    Abstract: GVT71512D18
    Text: 7C1360A/GVT71256D36 7C1362A/GVT71512D18 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz


    Original     		PDF CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 36/512K CY7C1360A/GVT71256D36 CY7C1362A GVT71512D18

    ATPA

    Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
    Text: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C


    Original     		PDF CY2147-35C CY7C147-35C CY7C147-45C CY91L22-35C CY7C122-35C CY2147-45C CY7C148-35C CY7C148-25C+ ATPA 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c

    CY7C136-55NI

    Abstract: cy7c136 CY7C132 CY7C142 CY7C146 CY7C146-15NC CY7C136-25JXC CY7C136-55NC
    Text: CY7C132, 7C136 7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells that enable simultaneous reads of the same memory location ■ 2K x 8 organization ■ 0.65 micron CMOS for optimum speed and power


    Original     		PDF CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 CY7C136, CY7C136-55NI cy7c136 CY7C132 CY7C142 CY7C146 CY7C146-15NC CY7C136-25JXC CY7C136-55NC

    GVT71256B36TA-7

    Abstract: GVT71256B36T-7 CY7C1361A-100AI
    Text: 361A 7C1361A/GVT71256B36 7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Flowthrough Burst SRAM Features • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip


    Original     		PDF CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 36/512K GVT71256B36TA-7 GVT71256B36T-7 CY7C1361A-100AI

    Untitled

    Abstract: No abstract text available
    Text: 7C1360A/GVT71256D36 7C1362A/GVT71512D18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining


    Original     		PDF CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 36/512K

    CY7C1360

    Abstract: CY7C1360V25 CY7C1362V25 CY7C1364V25 intel 80.82
    Text: 7C1360V25 7C1362V25 7C1364V25 PRELIMINARY 256K x 36/256K x 32/512K x 18 Pipelined SRAM Features • Supports 200-MHz bus • Fully registered inputs and outputs for pipelined operation • Single 2.5V power supply • Fast clock-to-output times — 3.1 ns for 200-MHz device


    Original     		PDF CY7C1360V25 CY7C1362V25 CY7C1364V25 36/256K 32/512K 200-MHz 166-MHz 133-MHz 100-MHz CY7C1360 CY7C1360V25 CY7C1362V25 CY7C1364V25 intel 80.82

    81c78

    Abstract: 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference
    Text: Product Line Cross Reference CYPRESS 2147-35C 2147-45C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35C 2148-35M 2148-45C 2148-45C 2148-45M 2148-45M+ 2148-55C 2148-55C 2148-55M 2149-35C 2149-35C 2149-35M 2149-45C 2149-45M 2149-45M 2149-55C 2149-55C 2149-55M


    Original     		PDF 2147-35C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35M 2148-45C 81c78 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference

    CY7C136-55NI

    Abstract: CY7C146 idt7132 CY7C132 CY7C136 PC TO IDT7132 CY7C136-55NC
    Text: CY7C132/7C136 CY7C142/CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns


    Original     		PDF CY7C132/CY7C136 CY7C142/CY7C146 65-micron CY7C132/CY7C136 CY7C132/CY7C136; 52-pin 48-pin CY7C132/142) CY7C136-55NI CY7C146 idt7132 CY7C132 CY7C136 PC TO IDT7132 CY7C136-55NC

    CY7C1361V25

    Abstract: CY7C1363V25 CY7C1365V25
    Text: 329 7C1361V25 7C1363V25 7C1365V25 PRELIMINARY 256K x 36/256K x 32/512K x 18 Flowthrough SRAM Features • Supports 113-MHz bus operations • 256K x 36 / 256K x 32 / 512K x 18 common I/O • Fast clock-to-output times — 7.5 ns for 117-MHz device


    Original     		PDF CY7C1361V25 CY7C1363V25 CY7C1365V25 36/256K 32/512K 113-MHz 117-MHz 100-MHz 80-MHz 100-pin CY7C1361V25 CY7C1363V25 CY7C1365V25

    CY7C136E

    Abstract: CY7C131AE-15JXI CY7C136AE-55NXI
    Text: CY7C131E, CY7C131AE 7C136E, 7C136AE 1 K / 2 K x 8 Dual-port Static RAM 1 K / 2 K × 8 Dual-port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K / 2 K × 8 organization


    Original     		PDF CY7C131E, CY7C131AE CY7C136E, CY7C136AE CY7C131E CY7C136E CY7C136AE CY7C131AE-15JXI CY7C136AE-55NXI

    CY7C1367A

    Abstract: GVT71512C18 4947a
    Text: 7C1366A/GVT71256C36 7C1367A/GVT71512C18 256K x 36/512K x 18 Synchronous Pipelined SRAM Features 18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a


    Original     		PDF CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 36/512K 100-Pin 1-85050-A 119-Lead CY7C1367A GVT71512C18 4947a

    C13220

    Abstract: C1328 C1327 CY7C132 CY7C136 CY7C146 C1323 CY7C136-55NC
    Text: CY7C132/7C136 CY7C142/CY7C146 2K x 8 DualĆPort Static RAM output enable OE . BUSY flags are proĆ vided on each port. In addition, an interĆ rupt flag (INT) is provided on each port of the 52Ćpin LCC and PLCC versions. BUSY signals that the port is trying to access the


    Original     		PDF CY7C132/CY7C136 CY7C142/CY7C146 52pin CY7C132/ CY7C136; C13220 C1328 C1327 CY7C132 CY7C136 CY7C146 C1323 CY7C136-55NC

    Untitled

    Abstract: No abstract text available
    Text: CY7C132/7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM Features Functional Description • 0.8-raicron CMOS for optimum speed/power • BÜSŸ output flag on CY7C132/ 7C136; BUSY input on CY7C142/CY7C146 The CY7C132/CY 7C136/CY7C142/


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/ CY7C136; CY7C132/CY 7C136/CY7C142/ 7C146 7C136

    HA 13645

    Abstract: acr38
    Text: CY7C132/7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM Features Functional Description • 0.8-micron CM OS for optimum speed/power • BUSY output flag on CY7C132/ 7C136; BUSY input on CY7C142/CY7C146 The CY7C132/CY 7C136/CY7C142/


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/ CY7C136; 52-pin twfil24! HA 13645 acr38

    CY7C1361V25

    Abstract: CY7C1363V25
    Text: C Y 7 C 1 3 6 1 V 25 C Y 7 C 1 3 6 3 V 25 PRELIMINARY ~= C Y P H hbb = 256K x 36 / 512K x 18 Flowthrough SRAM Functional Description Features • Supports 113-MHz bus operations The 7C1361V25 and 7C1363V25 are 2.5v, 256K x 36 and 512K x 18 synchronous-flowthrough SRAM designed to


    OCR Scan     		PDF CY7C1361V25 CY7C1363V25 113-MHz 117-MHz 100-MHz 80-MHz 100-pin CY7C1361V25 CY7C1363V25

    Untitled

    Abstract: No abstract text available
    Text: fax id: 5201 CY7C132/7C136 CY7C142/CY7C146 W CYPRESS 2Kx8 Dual-Port Static RAM Features Functional Description True Dual-Ported memory cells which allow sim ulta­ neous reads of the same mem ory location 2K x 8 organization 0.65-micron CMOS for optimum speed/power


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 65-micron CY7C132/CY7C136 CY7C132/CY7C136; 52-pin 48-pin CY7C132/142)

    Z1213

    Abstract: CY7C132 CY7C136 CY7C146 zl12
    Text: bSE » CYPRESS SEMICONDUCTOR SSÖ'lbbE 0 0 0 ^ 7 4 7 ISb I CYP CY7C132/7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM output enable OE . BUSY flags are pro­ vided on each port. In addition, an interrupt Functional Description Features


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 CY7C142/CY7C146 CY7C132/ CY7C136; 52-pin CY7C132/CY7C136/CY7C142/ CY7C146 Z1213 CY7C132 CY7C136 zl12

    CY7C136

    Abstract: CY7C132 CY7C146 2Kx8 Dual-Port Static RAM z1013 CY7C132-55PI CY7C136-55NC
    Text: fax id: 5201 C Y 7 C 1 3 2 /C Y 7 C 1 3 6 C Y 7 C 1 4 2 /C Y 7 C 1 4 6 2Kx8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow sim ulta­ neous reads of the sam e memory location • 2K x 8 organization • 0.65-micron CMOS fo r optimum speed/power


    OCR Scan     		PDF 65-micron CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/CY7C136; 52-pin 48-pin CY7C132/142) CY7C136 CY7C132 CY7C146 2Kx8 Dual-Port Static RAM z1013 CY7C132-55PI CY7C136-55NC

    b1l3

    Abstract: CV7C136 CY7C1361V25 CY7C1363V25 CY7C1365V25 7C1361-133
    Text: ^ _ 5r^ C Y P R F .S S 7C1361V25 7C1363V25 7C1365V25 PBEUm m m 256K x36/256K x 32/512K x 18 Flowthrough SRAM Features • Supports 113-MHz bus operations • 256K x 36 / 256K x 32/512K x 18 common I/O » Fast clock-to-output times — 7.5 ns lor 117-MHz device


    OCR Scan     		PDF CY7C1361V25 CY7C1363V25 CY7C1365V25 36/256K 32/512K 113-MHz 117-MHz 100-MHz 80-MHz 100-pin b1l3 CV7C136 CY7C1361V25 CY7C1363V25 CY7C1365V25 7C1361-133

    C-136B

    Abstract: No abstract text available
    Text: CY7C132/7C136 CY7C142/CY7C146 CYPRESS 2K x 8 Dual-Port Static RAM F ea tu res F u n ctio n al D escrip tio n • 0 .8 -m icro n C M O S for optim u m speed/ pow er • A u to m atic power-down • T T L com p atib le • C ap ab le o f w ith stan d in g g re a te r th an


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 C-136B

    30l3l

    Abstract: No abstract text available
    Text: CY7C132/7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR F eatures F unctional D escription • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable of withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 MASTERCY7CI32/CY7C136 CY7C132/ CY7C136; 52-pin CY7C142/CY7C146 30l3l

    HA 13645

    Abstract: No abstract text available
    Text: fax id: 5201 CY7C132/7C136 CY7C142/CY7C146 2Kx8 Dual-Port Static RAM Featu res Functional Description • True Dual-Ported memory cells which allow sim ulta­ neous reads of the same memory location • 2K x 8 organization • 0.65-micron CMOS for optimum speed/power


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 65-micron Y7C142/CY7C146 CY7C132/CY7C136; CY7C142/CY7C146 52-pin 48-pin CY7C132/142) HA 13645