LPKG
Abstract: No abstract text available
Text: I/O Buffer Information Q L8xl2B, QL12xl6B, QL16x24B Components: QL8x12B, QL12x16B, QL16x24B VOL vs IOL VOH vs lOH V -5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 6.0 7.0 8.0 9.0 10.0 IOH Min -32.4 -30.6 -30.2 -29.7 -28.4 -27.0 -24.8 -22.1 -17.6 -12.6 -6.8
|
OCR Scan
|
QL12xl6B,
QL16x24B
QL8x12B,
QL12x16B,
24x32B
LPKG
|
PDF
|
Untitled
Abstract: No abstract text available
Text: I/O Buffer Information QL8xl2B, QL12xl6B, QL16x24B Components: QL8x12B, QL12x16B, QL16x24B Signals: All I/O pins. Please contact the QuickLogic Hotline 408 990-4100 for more information. VOL vs IOL IOL Min -24.3 -23.4 -22.5 -21.6 -20.7 0.0 18.9 35.6 47.3
|
OCR Scan
|
QL12xl6B,
QL16x24B
QL8x12B,
QL12x16B,
QL16x24B
24x32B
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Q L 8X 12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS Very High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. . 1,000 usable ASIC gates,
|
OCR Scan
|
8-by-12
44-pin
68-pin
100-pin
16-bit
|
PDF
|
QL12x16B
Abstract: ic 236
Text: Q L12x16B WildCat 2000 Very-High-Speed 2K 6K Gate CMOS FPGA pASIC HIGHLIGHTS .6000 total available gates, 88 input pins Q Very High Speed - ViaLink metal-to-metal programmable-via anti-fuse technology, allows counter speeds over 150 MHz and logic cell delays of
|
OCR Scan
|
L12x16B
12-by-16array
68and
84-pin
100-pin
QL12xl6
16-bit
QL12x16B
12xl6B
ic 236
|
PDF
|
Untitled
Abstract: No abstract text available
Text: QL12X16B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS Very High Speed - ViaLink® metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. High Usable Density - A 12-by-16 array of 192 logic cells
|
OCR Scan
|
QL12X16B
12-by-16
68-pin
84-pin
100-pin
16-bit
12x16B
PF100
M/883C
|
PDF
|
CPGA144
Abstract: No abstract text available
Text: QL16X24B pASIC 1 FAMILY Very-High-Speed 4K 12K Gate CMOS FPGA PRELIMINARY DATA pASIC HIGHLIGHTS .4000 usable gates, 122 input pins B Very High Speed - ViaLink metal-to-metal programmable-via anti fuse technology, allows data path speeds over 150 MHz, and logic cell
|
OCR Scan
|
QL16X24B
16-by-24
QL16x24B
QL16x24
CPGA144
|
PDF
|
Untitled
Abstract: No abstract text available
Text: QL12x16B W ildCat 2000 Very-High-Speed 2K 6K Gate CMOS FPGA pASIC HIGHLIGHTS Very High Speed - ViaLink metal-to-metal programmable-via anti-fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. B High Usable Density - A 12-by-16 array of 192 logic cells provides 6000
|
OCR Scan
|
QL12x16B
12-by-16
68and
84-pin
100-pin
12xl6
12xl6B
|
PDF
|
ACT1020 fpga
Abstract: ACT1020
Text: Q L 12 x 1 6 pA SIC 1 FAMILY Very-High-Speed 2K 6K Gate CMOS FPGA E l Very High Speed - ViaLink metal-to-metal programmable-via anti fuse technology, allows counter speeds over 100 MHz, and logic cell delays of under 4 ns. B High Usable Density - A 12-by-16 array of 192 logic cells provides 6000
|
OCR Scan
|
L12x16
12-by-16
68-pin
100-pin
16-bit
12x16
ACT1020 fpga
ACT1020
|
PDF
|
Untitled
Abstract: No abstract text available
Text: QL16X24 pASIC 1 FAMILY Very-High-Speed 4K 12K Gate CMOS FPGA ADVANCE DATA pASIC HIGHLIGHTS .4000 useable gates H Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 100 MHz, and logic cell delays of undo: 4 ns.
|
OCR Scan
|
QL16X24
16-by-24
16-bit
84-pin
QL12xl6
|
PDF
|
Untitled
Abstract: No abstract text available
Text: QL12x16BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and
|
OCR Scan
|
QL12x16BL
12-by-16
68-pin
84-pin
100-pin
QL12xl6B
12x16BL
PF100
|
PDF
|
Untitled
Abstract: No abstract text available
Text: QL12x16B WildCat 2000 Yery-High-Speed 2K 6K Gate CMOS FPGA Rev B pASIC HIGHLIGHTS .2000 usable gates, 88 I/O pins Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.
|
OCR Scan
|
QL12x16B
12-by-16
68pin
84-pin
100-pinCQFP,
100-pin
100pin
16-bit
12xl6B
|
PDF
|
QuickLogic ql16x24b-1pl84c
Abstract: No abstract text available
Text: QL16X24B WildCat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA pASIC HIGHLIGHTS B Very High Speed - ViaLink metal-to-metal programmable-via anti fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. H High Usable Density - A 16-by-24 array of 384 logic cells provides
|
OCR Scan
|
QL16X24B
16-by-24
84-pin
144-pin
169-pin
16-bit
QL16x24B
16x24B
QuickLogic ql16x24b-1pl84c
|
PDF
|
ACT1020
Abstract: QL12X16-1PL68C ACT1020 pga pl68c ACT1020 fpga
Text: bSE D flUICK LOGIC RQD3Q3D 00DQ057 b4T M ü l l I C QL12X16 pASIC 1 FAMILY Very-High-Speed 2K 6K Gate CMOS FPGA pASIC HIGHLIGHTS B Very H igh Speed - ViaLink metal-to-metal progranunable-via anti fuse technology, allows counter speeds over 100 MHz, and logic cell
|
OCR Scan
|
00DQ057
QL12X16
12-by-16
68-pin
100-pin
16-bit
12x16
ACT1020
QL12X16-1PL68C
ACT1020 pga
pl68c
ACT1020 fpga
|
PDF
|
PL84C
Abstract: CPGA Package Diagram TQFP 10 10
Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins Very High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.
|
OCR Scan
|
QL16x24B
16-by-24
84-pin
100-pin
144-pin
160-pin
16-bit
16x24B
PF144C
PL84C
CPGA Package Diagram
TQFP 10 10
|
PDF
|