QL3006 Search Results
QL3006 Datasheets (1)
Part | ECAD Model | Manufacturer | Description | Curated | Datasheet Type | PDF Size | Page count | |
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QL3006 |
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Pasic High-Speed Low Power | Original | 180.47KB | 17 |
QL3006 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: QL3006 pASIC 3 FPGA Data Sheet •••••• 6,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance and High Density • 6,000 usable PLD gates with 82 I/Os • 300 MHz 16-bit counters, 400 MHz datapaths |
Original |
QL3006 16-bit | |
asynchronous fifo vhdl
Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024
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Original |
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pasic 3
Abstract: QL3004-1PL68C QL3004 QL3004E QL3004-1PL84C QL3006 QL3012 QL3025 QL3040 QL3060
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Original |
16-bit pasic 3 QL3004-1PL68C QL3004 QL3004E QL3004-1PL84C QL3006 QL3012 QL3025 QL3040 QL3060 | |
QL3004
Abstract: QL3004-1PL68C QL3004E QL3012 QL3004-1PL84C QL3006 QL3025 QL3040 QL3060
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Original |
16-bit QL3004 QL3004-1PL68C QL3004E QL3012 QL3004-1PL84C QL3006 QL3025 QL3040 QL3060 | |
QL3006Contextual Info: 4/ S$6,& 3*$ 'DWD 6KHHW 8VDEOH 3/' *DWH S$6,& )3*$ &RPELQLQJ +LJK 3HUIRUPDQFH DQG +LJK 'HQVLW\ 'HYLFH +LJKOLJKWV +LJK 3HUIRUPDQFH +LJK 'HQVLW\ 6,000 Usable PLD Gates with 82 I/Os 300 MHz 16-bit Counters, 400 MHz Datapaths |
Original |
16-bit QL3006 |