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    R S FLIP FLOP LATCH Search Results

    R S FLIP FLOP LATCH Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TCKE800NL Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 18 V, 5.0 A, Latch, WSON10B Visit Toshiba Electronic Devices & Storage Corporation
    TCKE812NL Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 18 V, 5.0 A, Latch, Fixed Over Voltage Clamp, WSON10B Visit Toshiba Electronic Devices & Storage Corporation
    TCKE712BNL Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 13.2 V, 3.65 A, Latch, Adjustable Over Voltage Protection, WSON10 Visit Toshiba Electronic Devices & Storage Corporation
    TCTH022AE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Push-pull type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH022BE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Open-drain type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation

    R S FLIP FLOP LATCH Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: TC4044BP/BF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4044BP,TC4044BF TC4044B Quad 3-State R/S Latch quad NAND R/S latch TC4044BP TC4044B the latches composed by four independent R/S flip-flop circuits. TC4044B fabricated with NAND gates is


    Original     		PDF TC4044BP/BF TC4044BP TC4044BF TC4044B TC4044BP DIP16-P-300-2 OP16-P-300-1

    Untitled

    Abstract: No abstract text available
    Text: s e m ic o n d u c t o r Revised November 1999 74AC374 • 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The AC/ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop


    OCR Scan     		PDF 74AC374 74ACT374 AC/ACT374

    Untitled

    Abstract: No abstract text available
    Text: S E M I C O N D U C T O R tm 74ABT374 Octal D-Type Flip-Flop with General Description The ABT374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output


    OCR Scan     		PDF 74ABT374 ABT374

    Untitled

    Abstract: No abstract text available
    Text: R C H II- D S E M IC O N D U C T O R tm 74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The LVQ374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered


    OCR Scan     		PDF 74LVQ374 LVQ374

    Untitled

    Abstract: No abstract text available
    Text: Preliminary S E M [ C O N D U C T O R TM 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear Preliminary General Description The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock (CP) and Clear


    OCR Scan     		PDF 74LVTH273 LVTH273

    74ABT374

    Abstract: 74ABT374CMSA 74ABT374CMTC 74ABT374CSC 74ABT374CSJ M20D MS-013 MSA20 MTC20
    Text: _ ' _ iM , 4 _ . Revised N ovem ber 1999 S E M I C O N D U C T O R TM 74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The AB T374 is an octal D -type flip-flop featuring separate D -type inputs for each flip-flop and 3-STATE outputs for


    OCR Scan     		PDF 74ABT374 ABT374 74ABT374 74ABT374CMSA 74ABT374CMTC 74ABT374CSC 74ABT374CSJ M20D MS-013 MSA20 MTC20

    Untitled

    Abstract: No abstract text available
    Text: M OTOROLA S EMICO ADUCTOR TECHNICAL DATA Advance Information M C100LVEL30 M C 100EL30 TYiple D Flip-Flop W ith S et and R eset The MC100LVEL30 is a triple master-slave D flip flop with differential outputs. The MC100EL30 is pin and functionally equivalent to the


    OCR Scan     		PDF MC100LVEL30 MC100EL30 C100LVEL30 100EL30 751D-04 1100MHz BR1330

    Untitled

    Abstract: No abstract text available
    Text: S E M I C O N D U C T O R Revised A ugust 1998 TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has indejDendent J, K, PRESET, CLEAR, and C LO C K inputs with Q,


    OCR Scan     		PDF 74LCX112 LCX112

    Untitled

    Abstract: No abstract text available
    Text: s e m ic o n d u c t o r Revised November 1999 74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The ABT374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Out­


    OCR Scan     		PDF 74ABT374 ABT374 74ABT374

    X112M

    Abstract: No abstract text available
    Text: Revised March 1999 S E M I C O N D U C T O R TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has indejDendent J, K, PRESET, CLEAR, and C LO C K inputs with Q,


    OCR Scan     		PDF 74LCX112 LCX112 X112M

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R Revised March 1999 TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has inde£endent J, K, PRESET, C LEAR , and C LO C K inputs with Q,


    OCR Scan     		PDF 74LCX112 LCX112

    Untitled

    Abstract: No abstract text available
    Text: Revised June 1998 S E M I C O N D U C T O R TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has indepen­ dent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q out­


    OCR Scan     		PDF 74LCX112 LCX112 74LCX112

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information M C100LVEL30 M C100EL30 Ttfple D Flip-Flop W ith S et and R eset The MC100LVEL30 is a triple master-slave D flip flop with differential outputs. The MC100EL30 is pin and functionally equivalent to the


    OCR Scan     		PDF C100LVEL30 C100EL30 MC100LVEL30 MC100EL30 751D-04 1100MHz BR1330 b3b7B52

    Untitled

    Abstract: No abstract text available
    Text: N T E ELECTRONICS INC 55E^D •! b4315ST 00QEfl74 MT7 H N T E - —INTEGRATEDCIRCUITS ^ TTb T R A N S IS T O R T R A N S IS T O R L O G IC Gated J-K Master-Slave 14-LeadDIP,SeeDiag.249 Dual J-K Neg Edge Flip-Flop Triggered Flip-Flop "/C lear - T - M 3 -Ô I


    OCR Scan     		PDF b4315ST 00QEfl74 14-LeadDIP 14-Lead 16-LeadDIP T-90-01

    74LCX112

    Abstract: 74LCX112M 74LCX112MTC 74LCX112SJ LCX112 M16A M16D MTC16
    Text: S E M IC O N D U C T O R Revised March 1999 TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features T he LCX112 is a dual J-K flip-flop. Each flip-flop has inde­ pendent J, K, PRESET, C LEAR, and C LO C K inputs with Q,


    OCR Scan     		PDF 74LCX112 LCX112 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ M16A M16D MTC16

    2SUR

    Abstract: CY7C331 L1190 C3317
    Text: CY7C331 ¿F C Y P R E S S Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set, reset, and clock inpnts on all


    OCR Scan     		PDF CY7C331 28-pin 40HMB CY7C331â 40LMB 28-Square 40QMB 2SUR L1190 C3317

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual D ifferen tial D ata and C lock D Flip-Flop W ith S e t and R eset MC100LVEL29 MC100EL29 The MC100LVEL29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The


    OCR Scan     		PDF MC100LVEL29 MC100EL29 MC100LVEL29 MC100EL29 DL140) b3b7252 DL140

    100LVEL29

    Abstract: 100el29 Ox25C Toggle flip flop IC
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual D ifferen tial D ata and C lock D Flip-Flop W ith S et and R eset M C 100LVEL29 M C 100EL29 The MC100LVEL29 is a dual m a ste r-sla ve flip flop. The device features fully differential Data and C lock inputs as well as outputs. The


    OCR Scan     		PDF MC100LVEL29 MC100EL29 100LVEL29 DL140) DL140 100el29 Ox25C Toggle flip flop IC

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm 74LCX374 Low Voltage Octal D Flip-Flop with 5V Tolerant Inputs and Outputs General Description Features The LCX374 consists of eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-STATE out­ puts for bus-oriented applications. A buffered clock CP and


    OCR Scan     		PDF 74LCX374 LCX374

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R 74LCX374 Low Voltage Octal D Flip-Flop with 5V Tolerant Inputs and Outputs General Description Features The LCX374 consists of eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-STATE out­ puts for bus-oriented applications. A buffered clock CP and


    OCR Scan     		PDF LCX374 74LCX374 2314-006I

    Untitled

    Abstract: No abstract text available
    Text: 74ACT11378 HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE S C A S 1 8 5 A - A U G U S T 1990 - R EVISED A P R IL 1993 DW OR N PACKAGE • Inputs Are TTL-Voltage Compatible TOP VIEW • Contains Six D-Type Flip-Flops


    OCR Scan     		PDF 74ACT11378 500-mA 300-mil

    Untitled

    Abstract: No abstract text available
    Text: TC4043BP TC4043BP C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC QUAD 3-STATE R/S LATCH Quad NOR R/S Latch TC4043BP is the latches composed by four independent R/S flip-flop circuits. TC4043BP fabricated with NOR gates is suitable for data processing of four bits


    OCR Scan     		PDF TC4043BP TC4043BP -300A

    Untitled

    Abstract: No abstract text available
    Text: if H A R R CD74FCT273 IS S E M I C O N D U C T O R January 1997 BiCMOS FCT Interface Logic, Octal D Flip-Flop with Reset t & SQSM& E 'Ni OrT w no\ogv Features Description • Buffered Inputs The CD74FCT273 octal D flip-flop with reset uses a small geometry BiCMOS technology. The output stage is a com­


    OCR Scan     		PDF CD74FCT273 CD74FCT273 700MHz

    Untitled

    Abstract: No abstract text available
    Text: 273 54F/74F273 Connection Diagrams Octal D Flip-Flop T— r ' - M R p ~ H rS rz a ht edge-triggered D-type flip-flops with individual D The common buffered Clock CP and Master Reset n ^ re s e i (clear) all flip-flops simultaneously. The register is full


    OCR Scan     		PDF 54F/74F273 54F/74F