E6G 6 PIN IC
Abstract: No abstract text available
Text: RGB528A 1.0 Microprocessor Access A s seen on the m icroprocessor b u s there are eight I/O addresses, selected by RS[2:0]. T w o indirect schem es are used to access all of the internal registers and a rra ys th ro u g h these eight p rim a ry I/O addresses.
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RGB528A
E6G 6 PIN IC
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Untitled
Abstract: No abstract text available
Text: RGB528A 1.0 Microprocessor Access As seen on the microprocessor bus there are eight I/O addresses, selected by RS[2:0], Two indirect schemes are used to access all of the internal registers and arrays through these eight primary I/O addresses. The first scheme is standard VGA, and operates when
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RGB528A
256x8
RGB528,
RGB528A
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Untitled
Abstract: No abstract text available
Text: RGB528A 8.0 Power Management The following registers are used to control power dissipation: □ Power Managem ent index 0x0005 □ Miscellaneous Clock Control (index 0x0002) □ Sync Control (index 0x0003) □ Miscellaneous Control 1 (index 0x0070) 8.3 Clocking Power
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RGB528A
0x0005)
0x0002)
0x0003)
0x0070)
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Untitled
Abstract: No abstract text available
Text: RGB528A 4.0 Controls 4.1 Blank and Border Control T h e B L A N K and B O R D E R / O E sig n a ls control the w ay in w hich data is presented to the D A C s. T h e se control sig n a ls are used to determ ine w he n pixel data is valid, w he n the border color is to be displayed, w here the cu r
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RGB528A
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Untitled
Abstract: No abstract text available
Text: RGB528A 12.0 Pin Descriptions Table 11. Pin Descriptions Signal Typ e Pin s Description Clocks and Clock Controls R EFCLK I 117 Reference Clock. A fixe d fre q u e n cy o f 2 M H z to 100 M H z a pplied to th is p in provides th e reference clock fo r th e p ro g ra m m a b le pixel and system clock
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RGB528A
PIX156)
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RGB514
Abstract: RGB528A
Text: RGB528A B.O Switching Into VGA Mode The RGB528A has two fundam ental modes of operation which depend on the input pixel port selected, VGA or V R A M . The port is selected w ith the "PORT SEL" bit bit 0 of Miscellaneous Control 2 register. But now set bits 7 and 6 to ’00' (PC LK SEL =
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RGB528A
RGB528A
RGB513,
RGB514,
RGB525
RGB514
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RGB525
Abstract: No abstract text available
Text: RGB528A Appendix O n th e RGB525 b it 4 o f th e P L L C o n tro l 1 re g iste r selects th e reference source o f th e P L L , R E F C L K or E X T C L K . On th e R G B 528A th is b it is reserved. A.0 Relationship to RGB525 B its 7 - 6 of th e M iscellaneous C o n tro l 2 register
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RGB528A
RGB525
RGB528A
RGB525
RGB525.
B528A
0x0090,
0x0091,
0x0092,
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rgb52
Abstract: No abstract text available
Text: RGB528A 11.0 Register Descriptions pixel Mask / 11.1 7 6 The direct access registers are addressed using RS[2:0] inputs. RS[2:0]: 010 Access: Read/Write Bits 7 - 0 6 5 4 3 2 1 / W RITE Address RS[2:0]: 000 Access: Read/Write Pow er on Value: Undefined Bits 7 - 0
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RGB528A
rgb52
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RGB525
Abstract: No abstract text available
Text: RGB528A 17.0 Change Summary Table 20. Summary of Changes Date Changes 05/09/94 1. F irs t p u b lica tio n . 07/20/94 1. C o rre cte d d e sc rip tio n o f pixe l P L L o p e ra tio n fo llo w in g a reset. Section 2.7.1, "Pixel P L L ," now in d ica te s
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RGB528A
37RGB528
RGB525
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RS-343-A
Abstract: RS-343A
Text: RGB528A 14.0 Video Waveforms ^ WHITE BLACK BLANK SYNC Table 17. Composite Video Output Waveform D o u b ly te rm in a te d 75 ohms, R R E F= 698 ohms Sync No Pedestal V alue No No IR E W H ITE V 18.65 0.70 IR E mA V 19.05 0.714 92.5 Yes No Yes mA 100 BLA C K
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RGB528A
RS-343A
RS-343-A
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B-528
Abstract: No abstract text available
Text: RGB528A C.O -A Revision Level 4. The original RGB528 is replaced with the "-A" revision RGB528A . The new revision has the following changes from the original: 1. The RG B528A has a bit in the Miscellaneous Clock Control register (index 0x0002) called S C L K INVT.
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RGB528A
RGB528
RGB528A)
B528A
0x0002)
0x0005)
0x0000)
B-528
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Untitled
Abstract: No abstract text available
Text: RGB528A 15.0 Package Information 1.110 28.30 _ 1094(27.80) 0 .122 ' (3 10) MAX 02850100010200020101000001010089000201010002 0.025 4' (0.635) 2.5^2 5'M AX ~ i r~ 0.011 (0.28) 0.007(0.18) 0.024 (0.60) 0.016(0.40) 0.023 (0.58) 0.016(0.42) 16.0 Ordering Information
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RGB528A
37RGB528
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Untitled
Abstract: No abstract text available
Text: RGB528A 13.0 Electrical and Timing Specifications Table 13. Recommended Operating Conditions 170 M H z P a ra m e te r 250 M H z U n its M in . Power Supply 220 M H z Sym bol M ax. M in . M ax. M in . M ax. VDD, DACVDD, PLLVDD 3.0 3.6 3.0 3.6 3.42 3.78 Volts
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RGB528A
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Untitled
Abstract: No abstract text available
Text: RGBS28A 7.0 Digital Outputs T he digital pixel data th a t is presented internally to the DACs is made available externally for driving fla t panel displays. There are two restrictions: □ □ The V R A M size cannot be 128, because the digital outputs are shared w ith the high 64
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RGBS28A
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