S21600FDS Search Results

half adder ttl

Abstract: MA914 MA92 non inverting buffer 8 volts via apollo vp GEC Marconi GEC Plessey m SHR8
Text: GEC PL ESS EY S I M I , O \ I I, I. T O MAMMA Sea of Gates Radiation Hard Advanced Gate Array Design System K -> S21600FDS Issue 1.2 Novem ber 1990 Features • Channelless array architecture • Typical gate delay 1 OnS - toggle rates of 100MHz achievable