Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    SCAS321 Search Results

    SCAS321 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit


    Original     		PDF CDC111 SCAS321G SCBA004C SDYA010 SDYA012 SCAA029, CDC111FN CDC111FNR

    CDC111

    Abstract: No abstract text available
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321F – SEPTEMBER 1993 – REVISED AUGUST 1996 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit


    Original     		PDF CDC111 SCAS321F CDC111

    CDC111

    Abstract: CDC111FN CDC111FNR MS-018
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit


    Original     		PDF CDC111 SCAS321G CDC111 CDC111FN CDC111FNR MS-018

    CDC111

    Abstract: CDC111FN CDC111FNR CDC111FNRG4 MS-018
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit


    Original     		PDF CDC111 SCAS321G CDC111 CDC111FN CDC111FNR CDC111FNRG4 MS-018

    Untitled

    Abstract: No abstract text available
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit


    Original     		PDF CDC111 SCAS321G

    Untitled

    Abstract: No abstract text available
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit


    Original     		PDF CDC111 SCAS321G

    CDC111

    Abstract: CDC111FN CDC111FNR MS-018
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit


    Original     		PDF CDC111 SCAS321G CDC111 CDC111FN CDC111FNR MS-018

    CDC111

    Abstract: No abstract text available
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321F – SEPTEMBER 1993 – REVISED AUGUST 1996 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit


    Original     		PDF CDC111 SCAS321F CDC111

    Untitled

    Abstract: No abstract text available
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit


    Original     		PDF CDC111 SCAS321G

    Untitled

    Abstract: No abstract text available
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit


    Original     		PDF CDC111 SCAS321G

    CDC111

    Abstract: MS-018
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit


    Original     		PDF CDC111 SCAS321G CDC111 MS-018

    SCAD004

    Abstract: CDC111 CDCVF111 SARONIX SCS
    Text: Application Report SCAA047 – October 2001 Jitter Performance of TI’s CDC111/CDCVF111 Kal Mustafa High Performance Analog/CDC ABSTRACT This application report discusses various jitter measurements of TI’s CDC111/CDCVF111 while being driven by three different clock sources VCXOs . The data contained in this


    Original     		PDF SCAA047 CDC111/CDCVF111 CDC111/CDCVF111 CDC111 CDCVF111 SCAD004 SARONIX SCS

    cdv304

    Abstract: capacitive coupling ethernet CDC111 CDCV304 CDCVF111 HPA8133A TLK3104SA
    Text: Application Report SCAA049 – November 2001 Using TI’s CDC111/CDCVF111 With TLK3104SA Serial Transceiver for Gigabit Ethernet and Backplane Applications Kal Mustafa High Performance Analog/CDC ABSTRACT This application report discusses jitter transfer of TI’s CDC111/CDCVF111 clock drivers


    Original     		PDF SCAA049 CDC111/CDCVF111 TLK3104SA TLK3104 TLK3104SA. cdv304 capacitive coupling ethernet CDC111 CDCV304 CDCVF111 HPA8133A

    CDC111

    Abstract: CDCV304 CDCVF111 SLK2501 capacitive coupling ethernet
    Text: Application Report SCAA050 – November 2001 Using TI’s CDCVF111 With SLK2501 Serial Gigabit Transceiver for SONET and Gigabit Ethernet Applications Kal Mustafa High Performance Analog/CDC ABSTRACT SONET/SDH and gigabit ethernet applications all have stringent timing requirements,


    Original     		PDF SCAA050 CDCVF111 SLK2501 CDCVF111, SLK2501, OC-48/24/12/3) CDC111 CDCV304 capacitive coupling ethernet

    SN74ALVCH162245

    Abstract: Schottky Barrier Diode Bus-Termination Array SN7400 CLOCKED SLLS210 SCAD001D TEXAS INSTRUMENTS SN7400 SERIES buffer SN74LVCC4245 sn74154 SDAD001C SN7497
    Text: Section 4 Logic Selection Guide ABT – Advanced BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 ABTE/ETL – Advanced BiCMOS Technology/ Enhanced Transceiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9


    Original     		PDF

    f741561

    Abstract: C139 CDC111 CDCVF111 R112
    Text: Application Report SCAA051 – November 2001 Output Jitter of CDC111/CDCVF111 in an ASIC Networking Application High Performance Analog/CDC Kal Mustafa ABSTRACT This report contains a number of peak-to-peak and cycle-to-cycle jitter measurements of TI’s CDC111 and CDCVF111 clock driver. In this ASIC event, both the


    Original     		PDF SCAA051 CDC111/CDCVF111 CDC111 CDCVF111 CDC111/CDCVF111. f741561 C139 R112

    SN74HC02 Spice model

    Abstract: philips semiconductor data handbook SDAD001C SDFD001B SCAD001D SN7497 spice model SN74AHC14 spice Transistor Crossreference SLLS210 ci ttl sn74ls00
    Text: LOGIC OVERVIEW 1 FUNCTIONAL INDEX 2 FUNCTIONAL CROSSĆREFERENCE 3 DEVICE SELECTION GUIDE 4 3 LOGIC SELECTION GUIDE FIRST QUARTER 1997 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest


    Original     		PDF

    CML Vterm

    Abstract: CDC111 CDCLVD110 CDCLVP110 CDCVF111 SN65LVDS101 SN65LVDT100 SN65LVDT122 SN65LVDT33 SN64LVDS33
    Text: Application Report SCAA059 – March 2003 AC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML Kal Mustafa/Chris Sterzik High Performance Analog ABSTRACT This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this report are lowvoltage positive-referenced emitter coupled logic LVPECL , low-voltage differential


    Original     		PDF SCAA059 CML Vterm CDC111 CDCLVD110 CDCLVP110 CDCVF111 SN65LVDS101 SN65LVDT100 SN65LVDT122 SN65LVDT33 SN64LVDS33

    SN65LVD100

    Abstract: Texas Instruments Application Report DC-Coupling TLK1501 SCAA059 scas683 SCAA056 SCAA062 CDC111 CDCVF111 SN65LVDS100
    Text: Application Report SCAA062 – March 2003 DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CM Kal Mustafa / Chris Sterzik High Performance Analog ABSTRACT This report describes various methods of interfacing different logic levels. The focus is dccoupling between the following differential signaling: LVPECL low-voltage positivereferenced emitter coupled logic , LVDS (low-voltage differential signals), HSTL (highspeed transceiver logic), and CML (current-mode logic). The report discusses sixteen


    Original     		PDF SCAA062 SN65LVD100 Texas Instruments Application Report DC-Coupling TLK1501 SCAA059 scas683 SCAA056 SCAA062 CDC111 CDCVF111 SN65LVDS100

    raaam

    Abstract: No abstract text available
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321 - SEPTEMBER 1993 - REVISED MARCH 1994 * Low Output Skew lor Clock-Distrlbution and Clock-Generatlon Applications * Differential Low Voltage Pseudo ECL LVPECL -Compatlble Inputs and Outputs * Distributes Differential Clock Inputs to Nine


    OCR Scan     		PDF CDC111 SCAS321 28-Pin raaam

    Untitled

    Abstract: No abstract text available
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321E - SEPTEMBER 1993 - REVISED APRIL 1996 Low-Output Skew for Clock-Dlstrlbution Applications Differential Low-Voltage Pseudo-ECL LVPECL -Compatlble Inputs and Outputs Distributes Differential Clock Inputs to Nine


    OCR Scan     		PDF CDC111 SCAS321E

    CDC111

    Abstract: No abstract text available
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321 - SEPTEMBER 1 9 9 3 - REVISED MARCH 1994 Low Output Skew for Clock-Distribution and Ciock-Generation Applications Differential Low Voltage Pseudo ECL LVPECL -Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine


    OCR Scan     		PDF CDC111 SCAS321 28-Pin CDC111

    Untitled

    Abstract: No abstract text available
    Text: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321F-SEPTEM BER 1993 - REVISED AUGUST 1996 * PN P A C K A G E L o w - O u t p u t S k e w for Clo ck -D is tri bu ti on TOP V IE W Applications * Differential L o w -V o lt a g e P s e u d o - E C L


    OCR Scan     		PDF CDC111 SCAS321F-SEPTEM