Untitled
Abstract: No abstract text available
Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V
|
Original
|
SN74ALVC32
SCES108G
24-mA
000-V
A114-A)
A115-A)
SN74ALVC32
scem245
|
PDF
|
apr 8910
Abstract: No abstract text available
Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108E – JULY 1997 – REVISED MARCH 2000 D D D D EPIC Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
|
Original
|
SN74ALVC32
SCES108E
MIL-STD-883,
SN74ALVC32PWR
SN74ALVC32
SCEM245,
apr 8910
|
PDF
|