A115-A
Abstract: C101 SN74AUC00
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
A115-A
C101
SN74AUC00
|
Untitled
Abstract: No abstract text available
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
|
Untitled
Abstract: No abstract text available
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 10 3B 9 3A 6 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
|
Untitled
Abstract: No abstract text available
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
|
A115-A
Abstract: C101 SN74AUC00
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
A115-A
C101
SN74AUC00
|
Untitled
Abstract: No abstract text available
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
|
ms00 marking
Abstract: No abstract text available
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
ms00 marking
|
A115-A
Abstract: C101 SN74AUC00
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
A115-A
C101
SN74AUC00
|
A115-A
Abstract: C101 SN74AUC00
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
A115-A
C101
SN74AUC00
|
Untitled
Abstract: No abstract text available
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
|
A115-A
Abstract: C101 SN74AUC00
Text: SN74AUC00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATE SCES510 − NOVEMBER 2003 D Optimized for 1.8-V Operation and Is 3.6-V D 1B 1Y 2A 2B 2Y 1A VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 10 3B 9 3A 6 7 8 3Y D D D D D I/O Tolerant to Support Mixed-Mode Signal Operation
|
Original
|
PDF
|
SN74AUC00
SCES510
000-V
A114-A)
A115-A)
A115-A
C101
SN74AUC00
|
Untitled
Abstract: No abstract text available
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
|
Untitled
Abstract: No abstract text available
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
|
A115-A
Abstract: C101 SN74AUC00
Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O
|
Original
|
PDF
|
SN74AUC00
SCES510A
000-V
A114-A)
A115-A)
A115-A
C101
SN74AUC00
|
|
PLL WITH VCO 4046 appli note philips
Abstract: CD74HC4050 marking microstar ms 4011 CI 40106 8952 microcontroller ic 4017 decade counter datasheet ic HC 4066 AG GK 7002 7 SEGMENT DISPLAY LT 543 PIN CONFIGURATION LA 4508 as af power amplifier
Text: LOGIC OVERVIEW 1 PRODUCT INDEX 2 FUNCTIONAL CROSS−REFERENCE 3 DEVICE SELECTION GUIDE 4 PACKAGING AND MARKING INFORMATION A LOGIC PURCHASING TOOL/ALTERNATE SOURCES B LOGIC SELECTION GUIDE FIRST HALF 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,
|
Original
|
PDF
|
|
hp laptop MOTHERBOARD pcb CIRCUIT diagram
Abstract: hp laptop battery pack pinout SCBD002C hp laptop battery pinout sn74154 SN74LVC1G373 SDFD001B 4052 IC circuit diagram lg crt monitor circuit diagram PLL CD 4046
Text: LOGIC OVERVIEW 1 PRODUCT INDEX 2 FUNCTIONAL CROSS−REFERENCE 3 DEVICE SELECTION GUIDE 4 PACKAGING AND MARKING INFORMATION A LOGIC PURCHASING TOOL/ALTERNATE SOURCES B LOGIC SELECTION GUIDE SECOND HALF 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,
|
Original
|
PDF
|
|