Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
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Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
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A115-A
Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542A – JANUARY 2004 – REVISED FEBRUARY 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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SN74SSTU32864C
25-BIT
SCES542A
14-Bit
A115-A
C101
SN74SSTU32864C
SN74SSTU32864CGKER
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A115-A
Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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Original
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PDF
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
A115-A
C101
SN74SSTU32864C
SN74SSTU32864CGKER
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Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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Original
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PDF
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
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Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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Original
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PDF
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
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Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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Original
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PDF
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
|
A115-A
Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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Original
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PDF
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
A115-A
C101
SN74SSTU32864C
SN74SSTU32864CGKER
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SSTL-18
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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Original
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PDF
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
SSTL-18
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S864C
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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Original
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PDF
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
S864C
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Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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Original
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PDF
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
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Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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Original
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PDF
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
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A115-A
Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
Text: SN74SSTU32864C 25ĆBIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES542 − JANUARY 2004 D Member of the Texas Instruments D D D D D D D Supports LVCMOS Switching Levels on the Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout
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Original
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PDF
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SN74SSTU32864C
25BIT
SCES542
25-Bit
14-Bit
A115-A
C101
SN74SSTU32864C
SN74SSTU32864CGKER
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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Original
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PDF
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
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