Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    SN54LV02 Search Results

    SN54LV02 Datasheets (14)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SN54LV02 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATES Original PDF
    SN54LV02 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATES Original PDF
    SN54LV02A Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATES Original PDF
    SN54LV02A Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATES Original PDF
    SN54LV02A Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATES Original PDF
    SN54LV02AFK Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATES Original PDF
    SN54LV02AFK Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATE Original PDF
    SN54LV02AJ Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATE Original PDF
    SN54LV02AJ Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATES Original PDF
    SN54LV02AW Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATES Original PDF
    SN54LV02AW Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATE Original PDF
    SN54LV02FK Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATE Original PDF
    SN54LV02J Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATE Original PDF
    SN54LV02W Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NOR GATE Original PDF

    SN54LV02 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J 000-V A114-A) A115-A) SN54LV02A LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390G – APRIL 1998 – REVISED OCTOBER 2002 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC 4Y 1 2 13 4Y 3 12 4B 4 11 4A 5 10 3Y 9 3B 6 7 8 SN54LV02A . . . FK PACKAGE


    Original     		PDF SN54LV02A, SN74LV02A SCLS390G 000-V A114-A) A115-A) SN54LV02A LV02A

    LV02A

    Abstract: A115-A C101 SN54LV02A SN74LV02A
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J SN54LV02A LV02A A115-A C101 SN54LV02A SN74LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J 000-V A114-A) A115-A) SN54LV02A LV02A

    A115-A

    Abstract: C101 LV02A SN54LV02A SN74LV02A
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J SN54LV02A A115-A C101 LV02A SN54LV02A SN74LV02A

    LV02A

    Abstract: SN54LV02A SN74LV02A
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390B – APRIL 1998 – REVISED JULY 1998 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV02A, SN74LV02A SCLS390B MIL-STD-883, SN54LV02A LV02A SN54LV02A SN74LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02, SN74LV02 QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D 1Y 1A 1B 2Y 2A 2B GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A SN54LV02 . . . FK PACKAGE


    Original     		PDF SN54LV02, SN74LV02 SCLS183B MIL-STD-883C, JESD-17 300-mil SN54LV02 SN74LV02

    lv02a

    Abstract: A115-A C101 SN54LV02A SN74LV02A
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J SN54LV02A lv02a A115-A C101 SN54LV02A SN74LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J 000-V A114-A) A115-A) SN54LV02A LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J 000-V A114-A) A115-A) SN54LV02A LV02A

    SN54LV02

    Abstract: SN74LV02
    Text: SN54LV02, SN74LV02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS183B – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV02, SN74LV02 SCLS183B MIL-STD-883C, JESD-17 300-mil SN54LV02 SN54LV02 SN74LV02

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J 000-V A114-A) A115-A) SN54LV02A LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J 000-V A114-A) A115-A) SN54LV02A LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02, SN74LV02 QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D 1Y 1A 1B 2Y 2A 2B GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A SN54LV02 . . . FK PACKAGE


    Original     		PDF SN54LV02, SN74LV02 SCLS183B SN54LV02 MIL-STD-883C,

    LV02A

    Abstract: SN54LV02A SN74LV02A
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390C – APRIL 1998 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV02A, SN74LV02A SCLS390C MIL-STD-883, LV02A SN54LV02A SN74LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J 000-V A114-A) A115-A) SN54LV02A LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390G – APRIL 1998 – REVISED OCTOBER 2002 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC 4Y 1 2 13 4Y 3 12 4B 4 11 4A 5 10 3Y 9 3B 6 7 8 SN54LV02A . . . FK PACKAGE


    Original     		PDF SN54LV02A, SN74LV02A SCLS390G 000-V A114-A) A115-A) SN54LV02A LV02A SN74LV02APWR

    A115-A

    Abstract: C101 LV02A SN54LV02A SN74LV02A
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390H – APRIL 1998 – REVISED JULY 2003 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC 4Y 1 2 13 4Y 3 12 4B 4 11 4A 5 10 3Y 9 3B 6 7 8 SN54LV02A . . . FK PACKAGE


    Original     		PDF SN54LV02A, SN74LV02A SCLS390H SN54LV02A A115-A C101 LV02A SN54LV02A SN74LV02A

    lv02a

    Abstract: A115-A C101 SN54LV02A SN74LV02A 74LV02A
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390D – APRIL 1998 – REVISED JANUARY 2001 D D D D 2-V to 5.5-V VCC Operation Typical VOLP Output Ground Bounce <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV02A, SN74LV02A SCLS390D 000-V A114-A) A115-A) SN54LV02A lv02a A115-A C101 SN54LV02A SN74LV02A 74LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J 000-V A114-A) A115-A) SN54LV02A LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390B – APRIL 1998 – REVISED JULY 1998 D EPIC  Enhanced-Performance Implanted D D D D 1Y 1A 1B 2Y 2A 2B GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A SN54LV02A . . . FK PACKAGE


    Original     		PDF SN54LV02A, SN74LV02A SCLS390B MIL-STD-883, SN54LV02A SN74LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J 000-V A114-A) A115-A) SN54LV02A LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC


    Original     		PDF SN54LV02A, SN74LV02A SCLS390J 000-V A114-A) A115-A) SN54LV02A LV02A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV02, SN74LV02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES S C L S 1 8 3 B - FEBRUARY 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vcc, Ta= 25°C Typical V q h v (Output Vqh Undershoot)


    OCR Scan     		PDF SN54LV02, SN74LV02 MIL-STD-883C, SN54LV02 SN74LV02 JESD-17