Untitled
Abstract: No abstract text available
Text: Package outline XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm 1 2 SOT1116 b 4 3 4x (2) L L1 e 8 7 e1 6 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e max 0.35 0.04 0.20 1.25 1.05
|
Original
|
PDF
|
OT1116
sot1116
|
MARKING V7 6-PIN
Abstract: No abstract text available
Text: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 11 — 6 July 2012 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
|
Original
|
PDF
|
74LVC3G14
74LVC3G14
MARKING V7 6-PIN
|
Marking code V7
Abstract: No abstract text available
Text: 74LVC2G00 Dual 2-input NAND gate Rev. 11 — 22 June 2012 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
|
Original
|
PDF
|
74LVC2G00
74LVC2G00
Marking code V7
|
74LVC2G86
Abstract: 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT
Text: 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 8 — 19 October 2010 Product data sheet 1. General description The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
|
Original
|
PDF
|
74LVC2G86
74LVC2G86
74LVC2G86DC
74LVC2G86DP
74LVC2G86GM
74LVC2G86GT
|
74LVC1G74DC
Abstract: 74LVC1G74 74LVC1G74DP 74LVC1G74GD 74LVC1G74GM 74LVC1G74GT
Text: 74LVC1G74 Single D-type flip-flop with set and reset; positive edge trigger Rev. 9 — 5 August 2010 Product data sheet 1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data D inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q
|
Original
|
PDF
|
74LVC1G74
74LVC1G74
74LVC1G74DC
74LVC1G74DP
74LVC1G74GD
74LVC1G74GM
74LVC1G74GT
|
74AUP2G157DC
Abstract: 74AUP2G157GT
Text: 74AUP2G157 Low-power 2-input multiplexer Rev. 4 — 30 July 2010 Product data sheet 1. General description The 74AUP2G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data
|
Original
|
PDF
|
74AUP2G157
74AUP2G157
74AUP2G157DC
74AUP2G157GT
|
74LVC3G07
Abstract: 74LVC3G07DC 74LVC3G07DP 74LVC3G07GM 74LVC3G07GT
Text: 74LVC3G07 Triple buffer with open-drain output Rev. 7 — 9 August 2010 Product data sheet 1. General description The 74LVC3G07 provides three non-inverting buffers. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
|
Original
|
PDF
|
74LVC3G07
74LVC3G07
74LVC3G07DC
74LVC3G07DP
74LVC3G07GM
74LVC3G07GT
|
74LVC2G32
Abstract: 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT XSON8 SOT1116
Text: 74LVC2G32 Dual 2-input OR gate Rev. 8 — 10 November 2010 Product data sheet 1. General description The 74LVC2G32 provides a 2-input OR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
|
Original
|
PDF
|
74LVC2G32
74LVC2G32
74LVC2G32DC
74LVC2G32DP
74LVC2G32GM
74LVC2G32GT
XSON8
SOT1116
|
74AUP2G241
Abstract: 74AUP2G241DC 74AUP2G241GT
Text: 74AUP2G241 Low-power dual buffer/line driver; 3-state Rev. 04 — 13 September 2010 Product data sheet 1. General description The 74AUP2G241 provides a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH
|
Original
|
PDF
|
74AUP2G241
74AUP2G241
74AUP2G241DC
74AUP2G241GT
|
74LVC2G126
Abstract: 74LVC2G126DC 74LVC2G126DP 74LVC2G126GD 74LVC2G126GM 74LVC2G126GT
Text: 74LVC2G126 Dual bus buffer/line driver; 3-state Rev. 9 — 13 September 2010 Product data sheet 1. General description The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input pin nOE . A LOW-level at pin nOE
|
Original
|
PDF
|
74LVC2G126
74LVC2G126
74LVC2G126DC
74LVC2G126DP
74LVC2G126GD
74LVC2G126GM
74LVC2G126GT
|
74AVC2T45
Abstract: 74AVC2T45DC 74AVC2T45GT
Text: 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 5 — 30 November 2010 Product data sheet 1. General description The 74AVC2T45 is a dual-bit, dual-supply transceiver that enables bidirectional level translation. It features two data input-output ports nA and nB , a direction control input
|
Original
|
PDF
|
74AVC2T45
74AVC2T45
74AVC2T45DC
74AVC2T45GT
|
Untitled
Abstract: No abstract text available
Text: 74AUP2G08 Low-power dual 2-input AND gate Rev. 5 — 1 December 2011 Product data sheet 1. General description The 74AUP2G08 provides the dual 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
|
Original
|
PDF
|
74AUP2G08
74AUP2G08
|
Dual D-type flip-flop positive-edge trigger
Abstract: No abstract text available
Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 6 — 8 December 2011 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the
|
Original
|
PDF
|
74AUP2G79
74AUP2G79
Dual D-type flip-flop positive-edge trigger
|
Untitled
Abstract: No abstract text available
Text: 74AUP2G38 Low-power dual 2-input NAND gate; open drain Rev. 6 — 9 December 2011 Product data sheet 1. General description The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to
|
Original
|
PDF
|
74AUP2G38
74AUP2G38
|
|
|
Untitled
Abstract: No abstract text available
Text: 74LVC3G04 Triple inverter Rev. 10 — 14 June 2012 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
|
Original
|
PDF
|
74LVC3G04
74LVC3G04
|
Untitled
Abstract: No abstract text available
Text: 74AUP1G885 Low-power dual function gate Rev. 8 — 8 June 2012 Product data sheet 1. General description The 74AUP1G885 provides two functions in one device. The output state of the outputs 1Y, 2Y is determined by the inputs (A, B and C). The output 1Y provides the Boolean
|
Original
|
PDF
|
74AUP1G885
74AUP1G885
|
Untitled
Abstract: No abstract text available
Text: 74AUP2G02 Low-power dual 2-input NOR gate Rev. 6 — 3 August 2012 Product data sheet 1. General description The 74AUP2G02 provides a dual 2-input NOR function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V o 3.6 V.
|
Original
|
PDF
|
74AUP2G02
74AUP2G02
|
Untitled
Abstract: No abstract text available
Text: 74LVC3GU04 Triple inverter Rev. 10 — 6 July 2012 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of
|
Original
|
PDF
|
74LVC3GU04
74LVC3GU04
JESD22-A114F
JESD22-A115-A
|
Untitled
Abstract: No abstract text available
Text: 74LVC2G00 Dual 2-input NAND gate Rev. 12 — 8 April 2013 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
|
Original
|
PDF
|
74LVC2G00
74LVC2G00
|
Untitled
Abstract: No abstract text available
Text: 74LVC1G53 2-channel analog multiplexer/demultiplexer Rev. 9 — 5 April 2013 Product data sheet 1. General description The 74LVC1G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device. The 74LVC1G53 provides one analog multiplexer/demultiplexer with a digital select
|
Original
|
PDF
|
74LVC1G53
74LVC1G53
|
Untitled
Abstract: No abstract text available
Text: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 12 — 9 April 2013 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
|
Original
|
PDF
|
74LVC3G14
74LVC3G14
|
Untitled
Abstract: No abstract text available
Text: 74LVC2G02 Dual 2-input NOR gate Rev. 11 — 8 April 2013 Product data sheet 1. General description The 74LVC2G02 provides a 2-input NOR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
|
Original
|
PDF
|
74LVC2G02
74LVC2G02
|
Untitled
Abstract: No abstract text available
Text: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 8 — 21 January 2013 Product data sheet 1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock
|
Original
|
PDF
|
74AUP2G80
74AUP2G80
|
Untitled
Abstract: No abstract text available
Text: 74AUP2G241 Low-power dual buffer/line driver; 3-state Rev. 7 — 11 February 2013 Product data sheet 1. General description The 74AUP2G241 provides a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH
|
Original
|
PDF
|
74AUP2G241
74AUP2G241
|
