SB865A
Abstract: SB866A ddr2 PLL JESD82 SSTUx32864 SSTU32868 JEDEC DDR2-400 2rx8 SB866 SN74SSTUB32866
Text: Application Report SCAA101 – March 2009 DDR2 Memory Interface Clocks and Registers – Overview Christian Schmoeller . CDC - Clock Distribution Circuits ABSTRACT This application report gives an overview of the existing JEDEC DDR2 Register and
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Original
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SCAA101
SB865A
SB866A
ddr2 PLL
JESD82
SSTUx32864
SSTU32868
JEDEC DDR2-400
2rx8
SB866
SN74SSTUB32866
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PDF
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DDR2-667
Abstract: SSTUB32869
Text: PRELIMINARY DATA SHEET 4GB VLP Registered DDR2 SDRAM DIMM EBE41AF4A1QA 512M words x 72 bits, 2 Ranks Specifications Features • Density: 4GB • Organization 512M words × 72 bits, 2 ranks • Mounting 18 pieces of 2G bits DDR2 SDRAM with DDP (FBGA)
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Original
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EBE41AF4A1QA
240-pin
667Mbps
M01E0706
E1165E10
DDR2-667
SSTUB32869
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PDF
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DDR2-667
Abstract: DDR2-800 E097
Text: PRELIMINARY DATA SHEET 4GB VLP Registered DDR2 SDRAM DIMM EBE41AF4A1QB 512M words x 72 bits, 2 Ranks Specifications Features • Density: 4GB • Organization 512M words × 72 bits, 2 ranks • Mounting 18 pieces of 2G bits DDR2 SDRAM with DDP (FBGA)
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Original
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EBE41AF4A1QB
240-pin
800Mbps/667Mbps
M01E0706
E1246E10
DDR2-667
DDR2-800
E097
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PDF
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