STD131 Search Results

DSPG

Abstract: Samsung Soc processor STD110 ASIC 16C450 16C550 ARM920T ARM940T IEEE1284 STD110 piler
Contextual Info: V S MSUNG STD131 ELECTRONICS STD131 Standard Cell 0.18um System-On-Chip ASIC Dec 2000, V2.0 Features 1.8/2.5/3.3V - Leff= 0.15um, Ldrawn = 0.18um Device - Up to 23 million gates - Power dissipation :24nW/MHz 3.3/5.0V - Gate Delay : 48ps @ 1.8V, 1SL Device

SL 220 YN 2

Abstract: MX2D2
Contextual Info: BUSHOLDER Cell List Cell Name BUSHOLDER Function Description Bus Holder Logic Symbol Cell Data Input Load SL Y 5.7 Y STD131 3-340 Gate Count 1.33 Samsung ASIC INTERNAL CLOCK DRIVERS Cell List Cell Name Function Description CK2 Internal Clock Driver CMOS 2mA

113 y

Abstract: HA 1329 QN-08 1329 y-448 AO2222
Contextual Info: Appendix Maximum Fanouts C Maximum Fanouts of Internal Macrocells Maximum Fanouts of Internal Macrocells When input tR/tF = 0.147ns, one fanout (SL = 0.00866pF) Cell Name ad2 ad2b ad2bd2 ad2bd4 ad2bd8 ad2d2 ad2d4 ad2d8 ad3 ad3d2 ad3d4 ad4 ad4d2 ad4d4 ad5

AO211

Abstract: IX 3354 AO222 ND2D2
Contextual Info: Revision History Based on Hard Copy . - First Edition(V1.0) : June 2001 • Chapter 1 : Introduction(V1.0) • Chapter 2 : DC Electrical Characteristics(V1.1) • Chapter 3 : Internal Macrocells(V2.1) • Chapter 4 : Input/Output Cells(V2.1) • Chapter 5 : Compiled Macrocells(V1.1)

CL 2181

Abstract: SL 1088 PHSOSCK17 PHSOSCK27
Contextual Info: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)

SAMSUNG 834

Contextual Info: Appendix Package Capabilities D Package Appendix D Package The most current package availability and capability can be obtained from your local Samsung Technology and Design Centers. • In-house ❏ Sub-contractor LQFP Package 0707 mm 1010 mm 1212 mm 1420 mm

RISC-Processor s3c2410

Abstract: MR16R1624DF0-CM8 arm9 samsung s3c2440 architecture chip 3351 dvd sp0411n K9W8G08U1M sandisk micro SD Card 2GB arm9 s3c2440 K9F1G08U0A K6X8008C2B
Contextual Info: A Section MEMORY Table of Contents SECTION A PAGE DRAM SDRAM 3a – 4a DDR SDRAM 5a – 6a DDR2 SDRAM 7a RDRAM 8a NETWORK DRAM 8a MOBILE SDRAM 9a GRAPHICS DDR SDRAM 10a DRAM ORDERING INFORMATION 11a –13a NAND FLASH COMPONENTS, SMART MEDIA, COMPACT FLASH

5v library

Abstract: STD130
Contextual Info: Input/Output Cells 4 Contents Summary Tables .4-2

samsung electrolytic capacitor

Abstract: frequency divider block diagram SAMSUNG DATASHEET CHIP CAPACITOR PLL2073X SAMSUNG CHIP CAPACITOR
Contextual Info: PLL 6 Contents PLL2073X . 6-1 PLL2073X General Description Features The PLL2073X is a Phase-Locked Loop PLL frequency synthesizer constructed in CMOS on a

AO222

Abstract: OA211 diode oa31 diode AO211 ND3B LD5Q AO2222 OA31 AO311 datasheet for full adder and half adder
Contextual Info: Internal Macrocells 3 Contents Overview . 3-1 Summary Tables. 3-2

Contextual Info: MIL-M-38510/220A USAF QU A L I F I C A T I O N REQUIREMENTS REMOVED MIL-M-38510/220ÎUSAF) 26 M a r c h 1979 MILITARY SPECIFICATION M I C R O C I R C U I T S , DIGI T A L , 8 1 9 2 BIT. MOS, U L T R A V I O L E T E RASABLE P R O G R A M M A B L E R E A D - O N L Y M E M O R Y (EPROM)

LD6QD2

Abstract: SL 220 TR 069 LD5Q LD4D2
Contextual Info: LATCHES Cell List Cell Name Function Description LD1 D Latch with Active High, 1X Drive LD1D2 D Latch with Active High, 2X Drive LD1Q D Latch with Active High, Q Output Only, 1X Drive LD1QD2 D Latch with Active High, Q Output Only, 2X Drive LD2 D Latch with Active High, Reset, 1X Drive

CL 2182

Abstract: CL 1221 cl 5403 A 1908 SL 2042 CMOS 4039
Contextual Info: INPUT BUFFERS Cell List Cell Name Function Description PIC/PICD/PICU 1.8V Interface CMOS Level Input Buffers PMIC/PMICD/PMICU 2.5V Interface CMOS Level Input Buffers PHIC/PHICD/PHICU 3.3V Interface LVCMOS Level Input Buffers PTIC/PTICD/PTICU 3.3V-tolerant for 1.8V Interface CMOS Level Input Buffers

tda 85630

Abstract: tda 7625 TDA 1007 tda 1282 tda 1700 bpw 104 tda 810 tda 1512 tda 266 TDA 452
Contextual Info: Compiled Memory 5 Contents Overview . 5-1 Compiled Memory Naming Convention. 5-1

sck 056

Abstract: jk flip flop SCK 055 SCK 206 datasheet d flip flop SCK 054 SCK 084 056
Contextual Info: FLIP-FLOPS Cell List Cell Name Function Description FD1 D Flip-Flop with 1X Drive FD1D2 D Flip-Flop with 2X Drive FD1CS D Flip-Flop with Scan Clock, 1X Drive FD1CSD2 D Flip-Flop with Scan Clock, 2X Drive FD1S D Flip-Flop with Scan, 1X Drive FD1SD2 D Flip-Flop with Scan, 2X Drive

Contextual Info: Appendix Glossary of Analog Terms A Digital-to-Analog Converter Digital-to-Analog Converter Appendix A 1. Resolution - An n-bit binary converter should be able to provide 2n distinct and different analog output values corresponding to the set of n-bit binary words. A

top 261 yn

Abstract: ARM9TDMI samsung display port verilog code for decimation filter TAG 8952 Bi-Directional P-Channel LPG CRT Power Supply schematic diagram samsung led SK 9080 verilog code for UART with BIST capability
Contextual Info: Introduction 1 Table of Contents 1.1 Library Description . 1-1 1.2 Features . 1-2

TDA 7588

Abstract: tda 7387 TDA 1157 TDA 2310 TDA 1038 TDA 3612 55320 tda 1171 240/tda 12122 tda 2253
Contextual Info: SPSRAM_LP Low-Power Single-Port Synchronous Static RAM Features Logic Symbol spsram_lp_<w>x<b>m<y> CK CSN WEN DOUT [b–1:0] OEN A [m-1:0] DI [b–1:0] NOTES: 1. Words w is the number of words. 2. Bpw(b) is the number of bits per word. 3. Ymux(y) is one of the column mux types.

B12 diode

Abstract: 3.3v to 5v buffer latch
Contextual Info: Electrical Characteristics 2 Contents DC Electrical Characteristics . 2-1 ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS VDD = 1.8V± 0.15V, TA = -40 to 85°C, VEXT = 3.3V ± 0.3V In case of 3.3V tolerant

AO222

Abstract: SL 220 AO211 AO22
Contextual Info: LOGIC CELLS Cell Names & Function Descriptions Cell Name Function Description AD2 2-Input AND with 1X Drive AD2D2 2-Input AND with 2X Drive AD2D4 2-Input AND with 4X Drive AD2D8 2-Input AND with 8X Drive AD2B 2-Input AND with one Inverted Input, 1X Drive AD2BD2