subtractor
Abstract: 8 bit subtractor AT40K AT40KAL AT94K
Text: IP Core Generator: Subtractor Features • Subtractor – Carry Select • Subtractor – Ripple Carry • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for • • • • FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices
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AT94K
AT40K
AT40KAL
AT94K
12/01/xM
subtractor
8 bit subtractor
AT40K
AT40KAL
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8 bit adder and subtractor
Abstract: full subtractor 4 bit binary full adder and subtractor 8 bit adder p345 8 bit carry adder ADDER
Text: Adder and Subtractor Macros Using Lattice Design Tools c4 = g3 + p3 . c3 = g3 + p3 g2 + p2 . g1 + p2 . p1 . g0 + p2. p1 . p0 . c0 Carry-Lookahead Adders Arithmetic logic blocks, such as adders and subtractors, are increasingly becoming performance bottlenecks in
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14-Bit
8 bit adder and subtractor
full subtractor
4 bit binary full adder and subtractor
8 bit adder
p345
8 bit carry adder
ADDER
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8 bit adder and subtractor
Abstract: 8 bit subtractor subtractor 8fadd 12 bits subtractor full adder full subtractor application application of full subtractor
Text: Application Brief 126 Subtractors in FLEX 8000 Devices Subtractors in FLEX 8000 Devices May 1994, ver. 1 Summary Files using the techniques described in this application brief are available from the Altera BBS at 408 954-0104 in the following self-extracting file:
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parallel Multiplier Accumulator based on Radix-2
Abstract: DS3707 PDSP16116 PDSP16116A PDSP16318A subtractor using TTL CMOS GG144 4 bit binary full adder and subtractor 32-bit adder block diagram for barrel shifter
Text: PDSP16116 16 X 16 Bit Complex Multiplier Supersedes October 1996 version, DS3707 - 4.2 The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications.
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PDSP16116
DS3707
PDSP16116
32-bit
PDSP16116A
PDSP16318A,
20MHz
20-bit
parallel Multiplier Accumulator based on Radix-2
PDSP16318A
subtractor using TTL CMOS
GG144
4 bit binary full adder and subtractor
32-bit adder
block diagram for barrel shifter
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AB126
Abstract: Adders ab118
Text: Application Brief 125 Designing Adders, Accumulators & Subtractors in FLEX 8000 Devices Designing Adders, Accumulators & Subtractors in FLEX 8000 Devices May 1994, ver. 1 Application Brief 125 Introduction FLEX 8000 devices feature look-up table LUT architecture and logic
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Z190
Abstract: voltage subtractor EN50081-2 EN50082-2 EN61010-1 DSAE006632
Text: CONVERTERS AND INTERFACES Z-LINE Z190 Standard converters Z-LINE DC Current / Voltage Adder - Subtractor ► INPUT: N.2 channels selectable in current 0.20, 4.20 mA or voltage 0.5, 1.5, 0.10, 2.10 Vdc ► OUTPUT: N.1 channel current 0.20, 4 . 20 mA
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EN50082-2
EN61010-1
Z190
voltage subtractor
EN50081-2
EN50082-2
EN61010-1
DSAE006632
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Untitled
Abstract: No abstract text available
Text: ESUM Two Encoder to One Encoder Adder/Subtractor Page 1 of 4 Description The ESUM combines the quadrature outputs of two encoders into a single quadrature output. The output quadrature may be selected to be either the sum or difference of the two quadrature inputs. The index from encoder 0 is simply
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FULL SUBTRACTOR using 41 MUX
Abstract: "Overflow detection"
Text: PDSP16318/16318A PDSP16318/PDSP16318A Complex Accumulator Advance Information Supersedes version DS3708 - 2.4 September 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and
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PDSP16318/16318A
PDSP16318/PDSP16318A
DS3708
PDSP16318/A
20-bit
20MHz
PDSP16318As
PDSP16112A
GC100
FULL SUBTRACTOR using 41 MUX
"Overflow detection"
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full subtractor
Abstract: 4 bit binary full adder and subtractor P345 G-345 g678 8 bit carry adder
Text: Adder and Subtractor Macros in ispEXPERT c4 = g3 + p3 . c3 = g3 + p3 g2 + p2 . g1 + p2 . p1 . g0 + p2. p1 . p0 . c0 Carry-Lookahead Adders Arithmetic logic blocks, such as adders and subtractors, are increasingly becoming performance bottlenecks in high-performance logic designs. Carry-lookahead adders
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14-Bit
full subtractor
4 bit binary full adder and subtractor
P345
G-345
g678
8 bit carry adder
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Untitled
Abstract: No abstract text available
Text: H D 10180 Dual 2-bit Adders/Subtractors The H D 1 0 1 8 0 is a high speed, lo w power, general- are Sum , Sum , and C arry-ou t. Th e com m on Select purpose adder/subtractor. Inputs fo r each adder inputs serve as a control line to invert A for are C arry-in, operand A , and operand B; outputs
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HD10180
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Untitled
Abstract: No abstract text available
Text: W tflGEC PLESSEY P R E L IM IN A R Y IN F O R M A T IO N DS3708 - 2.0 PDSP16318/PDSP16318A COMPLEX ACCUMULATOR The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz
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DS3708
PDSP16318/PDSP16318A
PDSP16318
20-bit
20MHz
PDSP16318As
PDSP16112A
256ps.
PDSP16318/13618A
PDSP16318/C0/AC
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8 bit adder and subtractor
Abstract: F10580 ECL ADDER adder H1211 F10180
Text: ; F10180 • F10580 / F10K VOLTAGE COMPENSATED ECL DUAL 2-BIT ADDER/SUBTRACTOR DESCRIPTION - The F10180/F10580 are high-speed, low-power Dual 2-Bit Adder/ Subtractors. It is designed to be used in special purpose adder/subtractors or in high speed multiplier arrays. Inputs for each adder are Carry-in, Operand A, and Operand B;
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F10180
F10580
F10180/F10580
8 bit adder and subtractor
F10580
ECL ADDER
adder
H1211
F10180
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bj 950 131- 6
Abstract: 74LS385 "serial adder" Am25LS14 serial adder AM25LS15PC bj 945 25ls22
Text: Am25LS15 Am25LS15 Quad Serial Adder/Subtractor DISTINCTIVE CHARACTERISTICS • • M a g n itu d e o n ly a d d itio n /s u b tra c tio n S e c o n d s o u rc e d b y T .l. a s A m 5 4 L S /7 4 L S 3 8 5 F o u r in d e p e n d e n t a d d e r/s u b tra c to rs
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Am25LS15
Am54LS/74LS385
Am25LS14
Am25LS
Am54LS/74LS
IC000180
03663B
bj 950 131- 6
74LS385
"serial adder"
serial adder
AM25LS15PC
bj 945
25ls22
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Untitled
Abstract: No abstract text available
Text: Am25LS15 Am25LS15 Quad Serial Adder/Subtractor DISTINCTIVE CHARACTERISTICS • • Magnitude only addition/subtraction Second sourced by T.l. as Am54LS/74LS385 Four independent adder/subtractors Use with two's complement arithmetic GENERAL DESCRIPTION The Am25LS15 is a serial two's complement adder/
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Am25LS15
Am54LS/74LS385
Am25LS14
Am25LS
Am54LS/74LS
IC000180
03663B
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Untitled
Abstract: No abstract text available
Text: Si GEC P L E S S E Y OCTOBER 1997 S E M I C O N D U C T O R S DS3707 - 5.3 P D S P 16 116 16X16 BIT COMPLEX MULTIPLIER Supersedes October 1996 version, DS3707 - 4.2 The PDSP16116 contains four 1 6 x1 6 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup
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DS3707
16X16
PDSP16116
32-bit
PDSP16116A
PDSP16318A,
20MHz
20-bit
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HD10180
Abstract: No abstract text available
Text: H D 10180 Dual 2-bit Adders/Subtractors The H D 1 0 1 8 0 is a high speed, lo w power, general purpose adder/subtractor. Inputs fo r each adder are Carry-in, operand A , and operand B; outputs • P IN a r r a n g e m e n t are Sum , Sum , and C arry-ou t. T h e com m on Select
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HD10180
HD10180----~
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Untitled
Abstract: No abstract text available
Text: ZW Ä N a t io n a l é H à S e m ic o n d u c t o r 54F/74F385 Quad Serial Adder/Subtractor General Description Features The 'F 3 8 5 co ntains fo u r serial a d d e r/su b tra cto rs w ith com mon clo ck and clea r inputs, but independent operand and
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54F/74F385
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Fast Fourier T
Abstract: adder ic serial adder adder subtractor
Text: Quad Serial Adder/Subtractor 25LS15 FEA TU R ES. • Fo u r Independent Adder/Subtractors ■ Use w ith Tw o's Com plem ent A rithm etic ■ M agnitude O n ly A d dition /Su btraction ■ Advanced Low -Pow er Sch o ttk y Processing ■ 100% R eliab ility Assurance Testing in Com p lian ce With
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25LS15
Fast Fourier T
adder ic
serial adder
adder subtractor
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logic diagram to setup adder and subtractor using
Abstract: No abstract text available
Text: Philips Components-Signetics 10180 Docum ent No. 8 5 3 -0 6 8 2 E C N No. 997 9 9 D ate of Issue June 14, 1990 Status Product Specification Adder/Subtractor Dual 2-Bit Adder/Subtractor EC L Products FEATURES ORDERING INFORMATION • Typical propagation delay: An, B„ to
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16-Pin
10180N
10180F
logic diagram to setup adder and subtractor using
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74LS385
Abstract: 54LS385
Text: SN54LS385, SN74LS385 QUADRUPLE SERIAL ADDERS/SUBTRACTORS D 2 41 2, N O VEM BER 197 7 - F o u r Synchro n o u s Elem ents in a Single 20-Pin Package R E V IS E D M A R C H 1 9 8 8 SN 54LS385 . . . J PACKAGE S N 74LS385 . . . DW OR N PACKAGE {TOP VIEW Buffered C lo ck and D irect C lear Inputs
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SN54LS385,
SN74LS385
20-Pin
LS385
SN54LS384/SN74LS384
74LS385
54LS385
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FULL SUBTRACTOR using 41 MUX
Abstract: DS3707 32 bit barrel shifter circuit diagram using multi bfp mark diode YI11 MT52L1G32D4PG-107 WT:B TR
Text: MITEL PD SP16116 16 X 16 Bit Complex Multiplier SEMICONDUCTOR Supersedes O ctober 1996 version, DS3707 - 4.2 DS3707 - 5.3 O ctober 1997 The PDSP16116 contains four 16x16 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup
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SP16116
DS3707
PDSP16116
16x16
32-bit
PDSP16116A
PDSP16318A,
20MHz
FULL SUBTRACTOR using 41 MUX
32 bit barrel shifter circuit diagram using multi
bfp mark diode
YI11
MT52L1G32D4PG-107 WT:B TR
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"Overflow detection"
Abstract: No abstract text available
Text: PDSP16318/PDSP16318A M ITEL Complex Accumulator SEMICONDUCTOR Supersedes version DS3708 - 2.4 Advance Inform ation Septem ber 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and
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PDSP16318/PDSP16318A
DS3708
PDSP16318/A
20-bit
20MHz
DSP16318As
PDSP16112A
16-bit
"Overflow detection"
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SN54LS385
Abstract: SN74LS385 54LS384 LS384
Text: SN54LS385, SN74LS385 QUADRUPLE SERIAL ADDERS/SUBTRACTORS SDLS170 Four Synchronous Elements in a Single 20-Pin Package D2412, N O VEM BER 1977 - SN 54LS385 R E V IS E D M A R C H 1 9 8 8 . . J PACKAGE S N 7 4 L S 3 8 5 . . . D W OR N P A C K A G E TO P V IE W
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SN54LS385,
SN74LS385
SDLS170
20-Pin
LS385
LS384/SN
LS384
SN54LS385
54LS384
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Untitled
Abstract: No abstract text available
Text: GEC P L E S S E Y DS3706 • 2.4 PDSP16318/PDSP16318 A COMPLEX ACCUMULATOR Supersedes version in December 1993 D igital Video & Video D igital Signal Processing 1C Handbook, HB3923-1 The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift
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DS3706
PDSP16318/PDSP16318
HB3923-1)
PDSP16318
20-bit
20MHz
PDSP16318As
PDSP16112A
PDSP16318/13618A
PDSP16318A/B0/AC
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