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    SY10H602JCTR Search Results

    SY10H602JCTR Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SY10H602JCTR Micrel Semiconductor 9 Bit Latched TTL-to-ECL Original PDF
    SY10H602JCTR Micrel Semiconductor 9-BIT LATCHED Original PDF
    SY10H602JC-TR Microchip Technology Integrated Circuits (ICs) - Logic - Translators, Level Shifters - IC TRNSLTR UNIDIRECTIONAL 28PLCC Original PDF
    SY10H602JCTR Synergy Semiconductor 9-BIT LATCHED TTL-TO-ECL Scan PDF

    SY10H602JCTR Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    100H602

    Abstract: SY100H602 SY10H602 SY10H602JC SY10H602JCTR
    Text: 9-BIT LATCHED TTL-TO-ECL SY10H602 SY100H602 DESCRIPTION FEATURES • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ Dual supply ■ 3.5ns max. D to Q ■ PNP TTL inputs for low loading


    Original     		PDF SY10H602 SY100H602 10Hxxx) 100Hxxx) MC10H/100H602 28-pin SY10/100H602 28-lead SY10H602JCTR J28-1 100H602 SY100H602 SY10H602 SY10H602JC SY10H602JCTR

    Untitled

    Abstract: No abstract text available
    Text: SY10H602 SY100H602 FINAL 9-BIT LATCHED TTL-TO-ECL DESCRIPTION FEATURES • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ Dual supply ■ 3.5ns max. D to Q ■ PNP TTL inputs for low loading


    Original     		PDF SY10H602 SY100H602 10Hxxx) 100Hxxx) MC10H/100H602 28-pin SY10/100H602 28-lead SY10H602JCTR J28-1

    SY100H602

    Abstract: SY10H602 SY10H602JC SY10H602JCTR
    Text: SYNERGY SY10H602 SY100H602 9-BIT LATCHED TTL-TO-ECL SEMICONDUCTOR SYNERGY SY10H602 SY100H602 SEMICONDUCTOR FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize


    Original     		PDF SY10H602 SY100H602 10Hxxx) 100Hxxx) MC10H/100H602 SY10/100H602 28-lead SY10H602JC SY100H602 SY10H602 SY10H602JC SY10H602JCTR

    SY100H602

    Abstract: SY10H602
    Text: • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ Dual supply ■ 3.5ns max. D to Q ■ PNP TTL inputs for low loading ■ Choice of ECL compatibility: MECL 10KH 10Hxxx


    Original     		PDF SY10H602 SY100H602 10Hxxx) 100Hxxx) MC10H/100H602 28-pin SY10/100H602 28-lead SY100H602 SY10H602

    Untitled

    Abstract: No abstract text available
    Text: 9-BIT L A T C H E D SYNERGY . TTL-TO-ECL - v . MHt . . S E M IC O N D U C T O R FEATURES • 9-bit ideal for byte-parity applications ■ Fully compatible with Motorola MC10H/100H602 The SY10/100H602 are 9-bit, dual supply TTL-to-ECL translators with latches. Devices in the Synergy 9-bit


    OCR Scan     		PDF 10Hxxx) MC10H/100H602 28-pin SY10/100H602 28-lead SY10H602JC SY10H602JCTR SY100H602JC SY100H602JCTR J28-1

    123 DAL

    Abstract: synergy series SY100H602 SY10H602 SY10H602JC q213
    Text: * 9-BIT LATCHED TTL-TO-ECL SYNERGY S E M IC O N D U C T O R FEATURES DESCRIPTION I 9-bit ideal for byte-parity applications T he SY 10/100H 602 are 9-bit, dual supply TTL-to-E C L tran sla to rs w ith latches. D evices in the S ynergy 9-bit tra n sla to r series utilize the 28-lead PLCC fo r optim al


    OCR Scan     		PDF SY10H602 SY100H602 10Hxxx) MC10H/100H602 SY10/100H602 28-lead SY10H602JC J28-1 SY10H602JCTR 123 DAL synergy series SY100H602 q213

    Untitled

    Abstract: No abstract text available
    Text: * 9-BIT LATCHED TTL-TO-ECL SYNERGY SY10H602 SY100H602 S E M IC O N D U C T O R FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ Dual supply


    OCR Scan     		PDF SY10H602 SY100H602 10Hxxx) MC10H/100H602 10/100H 28-lead SY10H602JC SY10H602JCTR SY100H602JC 100H602JCTR

    Untitled

    Abstract: No abstract text available
    Text: * SYNERGY 9-BIT LATCHED TTL-TO-ECL SY10H602 SY100H602 SEMICONDUCTOR FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ Dual supply ■ 3.5ns max. D to Q


    OCR Scan     		PDF SY10H602 SY100H602 10Hxxx) MC10H/100H602 28-pin SY10/100H602 28-lead

    Untitled

    Abstract: No abstract text available
    Text: * SYNERG Y 9-B IT LATCHED TTL-TO -EC L SY10H602 SY100H602 SEMICONDUCTOR FEATURES DESCRIPTION 9-bit ideal for byte-parity applications Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply 3.5ns max. D to Q PNP TTL inputs for low loading


    OCR Scan     		PDF SY10H602 SY100H602 10Hxxx) 100Hxxx) MC10H/100H602 28-pin SY10/100H602 28-lead

    Untitled

    Abstract: No abstract text available
    Text: * SYNERGY 9-BIT LATCHED TTL-TO-ECL SY10H602 SY100H602 SEMICONDUCTOR FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ Dual supply ■ 3.5ns max. D to Q


    OCR Scan     		PDF SY10H602 SY100H602 10Hxxx) MC10H/100H602 28-pin SY10/100H602 28-lead

    Untitled

    Abstract: No abstract text available
    Text: * 9 -B IT L A T C H E D SYNERGY T T L -T O -E C L SY10H602 SY100H602 SEMICONDUCTOR FEATURES DESCRIPTION 9-bit ideal for byte-parity applications Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply 3.5ns max. D to Q


    OCR Scan     		PDF SY10H602 SY100H602 10Hxxx) 100Hxxx) MC10H/100H602 SY10/100H602 28-lead SY10H602JC J28-1 SY10H602JCTR