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Abstract: No abstract text available
Text: TOSHIBA T C 5 5 V 1 1 6 5 F F -8 / 10/12 PRELIMINARY 65,536 WORD x 16 BIT SY NC HR ON OU S PIPELINE BURST SRAM Description The TC55V1165FF is a 1,048,576 bit synchronously pipelined burst SRAM that is organized as 65,536 w ords by 16 bits and designed for use in a secondary cache to support MPUs which have burst functions.
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TC55V1165FF
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Untitled
Abstract: No abstract text available
Text: TOSHIBA T C 5 5 V 1 1 6 5 F F -8 /1 0 /1 2 PRELIMINARY 65,536 WORD x 16 BIT SYNCHRONOUS PIPELINE BURST SRAM Description The TC55V1165FF is a 1,048,576 bit synchronously pipelined burst SRAM that Is organized as 65,536 words by 16 bits and designed for use in a secondary cache to support MPUs which have burst functions.
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TC55V1165FF
SR01011295
TC55V1165FF-8/10/12
LQFP100-P-1420)
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