FF100R12KS4
Abstract: No abstract text available
Text: Technische Information / technical information FF100R12KS4 IGBT-Module IGBT-modules 62mm C-Serien Modul mit schnellem IGBT2 für hochfrequentes Schalten 62mm C-Series module with the fast IGBT2 for high-frequency switching *+ , -) ./0 , 4 5 6 •8 5 9 :
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FF100R12KS4
FF100R12KS4
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MC68HC805C4
Abstract: MC68HSC05C4 68HC805 749u MC68HC05C4 MC68HC05C8 MC68 PC721 MC68HC05C2 motorola sf qfp
Text: ;I ,SPi,d I l,;M’l MC68HCOXP JIDT[lb MOTOROLA MC68HC05C4 Advance 8Mb 749U~=r~l-9 lnforma tion MC68HC05C2 MC68HSC05C4 MC68HC05C3 MC68HSC05C8 MC68HC05C8 MC68HC805C4 MC68HC705C8 [11 [2 [3) [41 [51 61 [71 (8] [91 [10) [11 pd?.yxb [2) ROM+z .+7’)b–*> Y?&A
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MC68HCOXP
MC68HC05C4
MC68HC05C2
MC68HSC05C4
MC68HC05C3
MC68HSC05C8
MC68HC05C8
MC68HC805C4
MC68HC705C8
MC68HC805C4
MC68HSC05C4
68HC805
749u
MC68HC05C4
MC68HC05C8
MC68
PC721
MC68HC05C2
motorola sf qfp
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CI 7805 pin diagram
Abstract: aui rj45 83C94 aui isolation transformer aui db15 to rj45 DTB 020 10MHZ LT6032
Text: 83C94 83C94 10BASE-T Twisted Pair Transceiver Technology Incorporated Septmeber 5, 1996 PRELIMINARY Features • Low Power CMOS Technology – 125 µA Standby typical Note: Check for latest Data Sheet revision before starting any designs. ■ Meets IEEE 802.3 10BASE-T standard for link
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83C94
10BASE-T
x3051.
8020/8023A
28-pin
MD400097/C
CI 7805 pin diagram
aui rj45
83C94
aui isolation transformer
aui db15 to rj45
DTB 020
10MHZ
LT6032
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pa 17105-1
Abstract: No abstract text available
Text: n m m n v iB in r REVISIONS —BRBWUM— RELEASED PER 9 7 -4 6 5 7 -0 1 2 w-i-w TS JW AD ;3 5PACE5 a 2.54 » 7.62 [.100] [.3003 A A IIUUüJNii MAILHJAL; t!ILRMOPLAÜI i C, COLOR-NA I URAL. A CONTACT FINISH: .0012?-.00254 I. 000050-.000100] NICKEL UNDERPLATE ALL OVER, .0007G [.0000301 GOLD PLATE IN
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0007G
0007B
oq77q|
pa 17105-1
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TXC-2 OSC
Abstract: 13fd7 txc 20.0 PEB2466H-V2.2-T/txc-
Text: NCR92C122 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUMS Symbol Parameter Minimum Maximum Units °C Ta Ambient Temperature 70 Ts Storage Temperature -55 125 °c VDD Supply Voltage -0.5 7.0 V V in Input Voltage -0.5 VDD + 0.5 Output Voltage -0.5 VUD + 0.5 V V
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NCR92C122
TXC-2 OSC
13fd7
txc 20.0
PEB2466H-V2.2-T/txc-
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se5021
Abstract: 2N3444 2N744 2N3606 PE5025 MPSH30 transistor 2N5134 cl-001 2N3252 2n3600
Text: This Material Copyrighted By Its Respective Manufacturer NATL SEniCOND 6501130 Sfl {DISCRETE} NATL SEMICOND, ÏËJhSD113D DISCRETE 2 8C 0ID353âS 35388 0/ << £ ti z 'a £« St'S y — œ u< <»'—£ûrEç * £Û u - y f > g CN CO CD — s n< O O c n c
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2N706
T0-18
2N743
2N744
2N753
se5021
2N3444
2N3606
PE5025
MPSH30 transistor
2N5134
cl-001
2N3252
2n3600
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Untitled
Abstract: No abstract text available
Text: NCR92C120 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUMS Symbol ta Ts Vdd V in VoUT tl Parameter Am bient Tem perature Storage Tem perature Supply Voltage Input Voltage O utput Voltage Lead Tem perature Soldering 10 seconds maximum Minimum Maximum 70 125 7.0
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NCR92C120
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MB1430
Abstract: 1431a MB1430A MB1431A 8202 dram controller baco MB81256-15 microprocessor 80286 internal block diagram MB1431 MB81C1000
Text: '7 I5 S3E FU J I T S U LTD 37 M T 7 S b 0 0 0 2 1 0 G DMT ì> £ c 3 3 ^ / IFCAJ February 1991 Edition 1.0 FUJITSU DATA SHEET '• MB1430A/1431A DYNAMIC RAM CONTROLLER LSI DYNAMIC RAM CONTROLLER The Fujitsu MB1430A and I431A are high-performance DRAM controtlen.
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MB1430A/1431A
MB1430A
I431A
MB1431A
374175b
MB1430
1431a
8202 dram controller
baco
MB81256-15
microprocessor 80286 internal block diagram
MB1431
MB81C1000
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w89c980p
Abstract: W89C980 RD7M
Text: W89C980 INTEGRATED MULTIPLE PORT REPEATER G E N E R A L D ESC R IPT IO N The Integrated Multiple Port Repeater IMPR implements the repeater functions specified by section 9 of the IEEE 802.3 standard and twisted pair line transceiver functions conforming to the 10BASE-T
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W89C980
10BASE-T
50-meter
W89C980
w89c980p
RD7M
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5 input nand gate
Abstract: MC830P MC932 MC832 MC835 mc1813 MC838 MC846 mc963g truth table for 7 inputs OR gate
Text: mm\L INTEGRATED CIRCUITS FROM MOTOROLA G MC830 Series 0 to +75°C MC930 Series (-55 to +125°) 2 [ M L IS S l E M D T L inte grated c irc u its p ro vid e an e x c e lle n t balance o f sc-eec p o w e r d is s ip a tio n , and noise im m u n ity fo r general purpose a o ta
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MC830
MC930
MC850/MC950
100pF)
MC950
5 input nand gate
MC830P
MC932
MC832
MC835
mc1813
MC838
MC846
mc963g
truth table for 7 inputs OR gate
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Untitled
Abstract: No abstract text available
Text: CY7C027/028 CY7C037/038 32K/64KX 16/18 Dual-Port Static RAM Fully asynchronous operation Automatic power-down Features • True Dual-Ported memory cells which allow simulta neous access of the same memory location • 32K x 16 organization CY7C027 • 64K x 16 organization (CY7C028)
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CY7C027/028
CY7C037/038
32K/64KX
CY7C027)
CY7C028)
CY7C037)
CY7C038)
35-micron
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Untitled
Abstract: No abstract text available
Text: CY7C027V/028V CY7C037V/038V PRELIMINARY 3.3 V 3 2 K /6 4 K X 16/18 Dual-Port Static RAM • Fully asynchronous operation Features • True Dual-Ported memory cells which allow simulta neous access of the same memory location • 32K x 16 organization CY7C027V
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CY7C027V/028V
CY7C037V/038V
CY7C027V)
CY7C028V)
CY7C037V)
CY7C038V)
35-micron
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Untitled
Abstract: No abstract text available
Text: 83C94 10BASE-T TWISTED PAIR TRANSCEIVER PRELIMINARY March 1992 Features • Low Power CMOS Technology - 125 \iA Standby typical ■ High-speed receiver architecture minimizes Jitter m Meets IEEE 802.3 10BASE-T standard for link Integrity, AUI and twisted pair squelch, collision
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83C94
10BASE-T
8020/8023A
MD400097/A
83C94
28-pin
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qml-38535
Abstract: 54ABT244 GDFP2-F20 smd "vhz"
Text: REVISIONS i DATE DESCRIPTION LTR APPROVED YR-MO-DA REV SHEET REV 15 SHEET 16 17 19 20 REV REV STATUS OF SHEETS 1 SHEET 2 Joseph A. Kerby STANDARDIZED MILITARY DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE
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QPL-38510.
QML-38535.
QML-38535
MIL-BUL-103.
MIL-BUL-103
54ABT244
GDFP2-F20
smd "vhz"
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93C94
Abstract: mau aui DTA 1006 TWISTED PAIR WIRE Valor pt3877 83C94 LT6032 b3c94 LAX-ET304
Text: G00Q 83C94 10BASE-T TWISTED PAIR TRANSCEIVER PRELIMINARY 1991 Features • L o w P o w e r CMOS T ech n o lo g y - 125 \lA S ta n d b y typ ica l ■ H ig h -spe e d re ce ive r a rc h ite c tu re m in im ize s Jitter ■ R ed u ce d th re s h o ld o p tio n fo r lo n g d ista n ce (20%
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10BASE-T
125\lA
8020/8023A
MD400097/-
83C94
83C94
28-pin
93C94
mau aui
DTA 1006
TWISTED PAIR WIRE
Valor pt3877
LT6032
b3c94
LAX-ET304
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AD588AD
Abstract: AD586 XW 3pin AD588SE AD586A AD586J AD586S AD586T AD588BD AD587
Text: ANALOG DEVICES High Precision 5V Reference AD586 □ FEATURES Laser Trimmed to High Accuracy: 5.000V ±2.0mV M Grade Trimmed Temperature Coefficient: 2ppm/°C max, 0 to +70°C (M Grade) 5ppm/°C max, -40°C to +85°C (B Grade) lOppmfC max, -55°C to + 125°C (T Grade)
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AD586
10ppm/Â
100nV/VHz
MIL-STD-883
AD680
AD680JN
AD680JR
AD680JT
AD588AD
XW 3pin
AD588SE
AD586A
AD586J
AD586S
AD586T
AD588BD
AD587
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tagl2
Abstract: S 0680 LR3000 DK3T TAG23 LR3000AKC33 lr3000gc20 MM7200 TAG24
Text: Chapter 12: Specifications This chapter presents the following information for the LR3000 and LR3000A processors: • LR3000 Electrical Specifications • LR3000A Electrical Specifications • Timing Diagrams • Mechanical, Pinout, and Mounting Information
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LR3000
LR3000A
144-pin
172-pin
tagl2
S 0680
DK3T
TAG23
LR3000AKC33
lr3000gc20
MM7200
TAG24
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yx 805 led driver
Abstract: YX 801 led driver 4 pins yx 801 led driver IC yx 801 led driver yx 805 led "yx 805" led driver yx 801 yx 801 led KSA itt LT6032 pulse TRANSFORMER
Text: 83C94 10BASE-T TWISTED PAIR TRANSCEIVER PRELIMINARY March 1992 Features • High-speed receiver erchltecture minimizes jitter ■ Low Power CMOS Technology - 125 p.A Standby typical U M n U IEEE 802.3 10BASE-T standard for link Integrity, AUI and twisted pair squelch, collision
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83C94
10BASE-T
8020/8023A
yx 805 led driver
YX 801 led driver 4 pins
yx 801 led driver
IC yx 801 led driver
yx 805 led
"yx 805" led driver
yx 801
yx 801 led
KSA itt
LT6032 pulse TRANSFORMER
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Untitled
Abstract: No abstract text available
Text: 155 Mbps ATM SAR CONTROLLER FOR PCI-BASED NETWORKING APPLICATIONS PRELIMINARY INFORMATION IDT77201 KEY FEATURES DESCRIPTION • Full-duplex Segmentation and Reassembly SAR at 155 Mbps "wire-speed" (310 Mbps aggregate speed). • Performs ATM layer protocol functions.
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IDT77201
66MHz
50MHz.
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w89c901
Abstract: W89C905 W89C902 w89c90 W89C925 BUT16
Text: W89C925 PENTIC IVinbond PCMCIA ETHERNET NETWORK TWISTED-PAIR INTERFACE CONTROLLER GENERAL DESCRIPTION The W89C925 PENTIC is a CMOS device designed for easy implementaion of PCMCIA R2.0/JEIDA 4.1 compatible CSMA/CD local area networks. TheW89C925 combines a W89C902 Serial LAN
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W89C925
TheW89C925
W89C902
10BASE2,
10BASE5,
w89c901
W89C905
w89c90
BUT16
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MAE 411
Abstract: No abstract text available
Text: £ ÿ j S G S -T H O M S O N STÌ3220 MOTION ESTIMATION PROCESSOR • PIXELRATE FROM 0 U P TO 20MHz ■ BLOCK SIZE : 8 x 4n, 16 x4n ■ MAXIMUM DISPLACEMENT +7/-8 PIXELS HORIZONTAL AND VERTICAL ■ COMPUTATION OF THE MOTION VECTOR AND MINIMUM DISTORTION ■ RANDOM ACCESS TO THE 256 DISTOR
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20MHz
16-BIT
20MHz
MAE 411
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W89C906
Abstract: W89C902
Text: W89C906 TWISTED-PAIR ETHER-LAN CONTROLLER WITH ISA INTERFACE H TELISA H GENERAL DESCRIPTION The TELISA II (Twisted-pair Ether-LAN Controller with ISA Interface II) integrates a W89C902 Serial LAN Coprocessor for Twisted-Pair (SLCT) and PC/AT ISA bus interface logic into a single chip. The
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W89C906
W89C902
NE2000
W89C906
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I1774
Abstract: No abstract text available
Text: HI-774 33 HARRIS 8/vs, Complete 12-Bit A/D Converter With Microprocessor Interface Description Features • C o m p le te 12 B it A /D C o n v e rte r W ith R e fe re n c e and C lo ck • D ig ita l E rro r C o rre c tio n • Full 8 -, 12-, o r 1 6 -B it M ic ro p ro c e s s o r B us In te rfa c e
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HI-774
12-Bit
I-774
28-pin
I1-774U
I1-774S
-774U
I4-774S
I4-774T
I1774
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W89C90
Abstract: CODER MANCHESTER DIFFERENTIAL HAO4 arbiter decoder -1996 w89c901
Text: Preliminary W89C926 PENTIC+ i.lV in b o n d ^ drHrtP1 E le c tro n ic s C orp . PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER GENERAL DESCRIPTION The W89C926 PENTIC+ is a CMOS device designed for easy implementation ot PCMCIA R2.1 compatible CSMA/CD local area networks. The W89C926 combines a W89C902 Serial LAN
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W89C926
W89C902
2-27S
86-5-S
CA95134,
43666S
4417S
6-2-71S
W89C90
CODER MANCHESTER DIFFERENTIAL
HAO4
arbiter decoder -1996
w89c901
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