STV0288
Abstract: ARGB1555 stx5105 stv0600 STi5107 st*0288 stv0288 I2C sti5107 jtag STi5107 pin out STV06000
Text: STi5107 Low-cost interactive set-top box decoder Data Brief Features – encoding of CGMS, Teletext, WSS, VPS, close caption • Enhanced ST20 32-bit VL-RISC CPU ■ Unified memory interface – up to166 MHz,16-bit wide SDR/DDR SDRAM interface ■ Programmable flash memory interface
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STi5107
32-bit
to166
16-bit
601/CCIR
STV0288
ARGB1555
stx5105
stv0600
STi5107
st*0288
stv0288 I2C
sti5107 jtag
STi5107 pin out
STV06000
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non interruptible and burst and memory
Abstract: CY7C1395V25
Text: CY7C1395 CY7C1395V25 PRELIMINARY 2M x 36 PBSRAM with NoBL-Burst Architecture Functional Description • Pin-compatible to ZBT™ and NoBL™ devices • Supports up to166-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate
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CY7C1395
CY7C1395V25
to166-MHz
166-MHz
133-MHz
100-MHz
CY7C1395/CY7C1395V25
non interruptible and burst and memory
CY7C1395V25
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stv6110A
Abstract: sti5107 jtag STI5107 stv6000 STi5105 STV06110A st*0288 STV0288 STV0362 ST20
Text: STi5107 Low-cost interactive set-top box decoder Data Brief Features • Enhanced ST20 32-bit VL-RISC CPU ■ Unified memory interface – up to166 MHz,16-bit wide SDR SDRAM interface ■ Programmable flash memory interface ■ Programmable transport interface PTI
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STi5107
601/CCIR
PBGA32
to166
16-bit
stv6110A
sti5107 jtag
STI5107
stv6000
STi5105
STV06110A
st*0288
STV0288
STV0362
ST20
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Untitled
Abstract: No abstract text available
Text: CDCVF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS637B – DECEMBER 1999 – REVISED JULY 2001 D D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible
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CDCVF2509
SCAS637B
PC133
PC133
24-Pin
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PDF
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Untitled
Abstract: No abstract text available
Text: Freescale Semiconductor Technical Data MSC8122 Rev. 6, 5/2005 MSC8122 Quad Core 16-Bit Digital Signal Processor SC140 Extended Core SC140 Extended Core SC140 Extended Core MQBus SC140 Extended Core 128 128 SQBus Boot ROM 64 Local Bus IP Master 32 Timers Memory
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MSC8122
16-Bit
SC140
RS-232
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PDF
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PC133 registered reference design
Abstract: No abstract text available
Text: CDCVF2509A www.ti.com SCAS765A – APRIL 2004 – REVISED JULY 2004 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE FEATURES FEATURES • • • • • • • • • • • • • • • • • • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification
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CDCVF2509A
SCAS765A
PC133
24-Pin
PC133 registered reference design
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stx5105
Abstract: cofdm transmitter jtag st TUNER transport stream stv0288 I2C ST20 Dolby S uc IR for Tx, RX set top box dvb STB6000
Text: STM5118 Low-cost interactive FTA set-top box decoder DATA BRIEF DESCRIPTION STMicroelectronics sets a new standard for performance, price and integration in the single chip MPEG-2 set-top-box decoder market with the introduction of the STM5118. This highly integrated
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STM5118
STM5118.
STM5118
stx5105
cofdm transmitter
jtag st
TUNER transport stream
stv0288 I2C
ST20
Dolby S
uc IR for Tx, RX
set top box dvb
STB6000
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PDF
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CY25560
Abstract: CY25561 CY25561SC CY25561SXC CY25561SXCT
Text: CY25561 Spread Spectrum Clock Generator Features Applications • 50 to 166 MHz Operating Frequency Range ■ Desktop, notebook, and tablet PCs ■ Wide Range of Spread Selections:9 ■ VGA controllers ■ Accepts Clock and Crystal Inputs ■ LCD panels and monitors
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CY25561
CY25560
CY25561
CY25561SC
CY25561SXC
CY25561SXCT
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Untitled
Abstract: No abstract text available
Text: Part Number 405EZ Revision 1.22 - February 21, 2007 405EZ Preliminary Data Sheet PowerPC 405EZ Embedded Processor Features • AMCC PowerPC 405 32-bit RISC processor core operating at up to 416MHz • IEEE 1588 Precision Timing Protocol PTP controller
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405EZ
405EZ
32-bit
416MHz
64-bit
166MHz
10-bit
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CDCVF2509A
Abstract: CDCVF2509APW CDCVF2509APWR PC133 registered reference design
Text: CDCVF2509A www.ti.com SCAS765A – APRIL 2004 – REVISED JULY 2004 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE FEATURES FEATURES • • • • • • • • • • • • • • • • • • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification
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CDCVF2509A
SCAS765A
PC133
PC133
24-Pin
CDCVF2509A
CDCVF2509APW
CDCVF2509APWR
PC133 registered reference design
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PDF
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PC133 registered reference design
Abstract: No abstract text available
Text: CDCVF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS637C − DECEMBER 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
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CDCVF2509
SCAS637C
CDCVF2509A
PC133
24-Pin
PC133 registered reference design
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PDF
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PC133 registered reference design
Abstract: No abstract text available
Text: CDCVF2510 www.ti.com SCAS638C – JULY 2001 – REVISED APRIL 2006 3.3-V PHASE-LOCK LOOP CLOCK DRIVER FEATURES • • • • • • • • • • • • • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible
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Original
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CDCVF2510
SCAS638C
PC133
24-Pin
PC133 registered reference design
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PDF
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Untitled
Abstract: No abstract text available
Text: CY25561 Spread Spectrum Clock Generator Features By doing this, the measured EMI at the fundamental and harmonic frequencies of clock SSCLK is reduced. • 50 to 166 MHz operating frequency range ■ Wide range of spread selections: 9 This reduction in radiated energy can significantly reduce the
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CY25561
CY25561
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AN 6682
Abstract: No abstract text available
Text: ICS9248-105 Integrated Circuit Systems, Inc. Preliminary Product Preview Frequency Generator & Integrated Buffers for Celeron & PII/III Recommended Application: ALI 1641 PII/PIII chip set. Output Features: • 2- CPUs @2.5V, up to 146.22MHz • 2 - AGPCLK @ 3.3V
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ICS9248-105
22MHz
to166MHz
48MHz
24MHz
318MHz
22MHz
175ps
400ps
AN 6682
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PDF
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Untitled
Abstract: No abstract text available
Text: Freescale Semiconductor Technical Data MSC8122 Rev. 10, 9/2005 MSC8122 Quad Core 16-Bit Digital Signal Processor SC140 Extended Core SC140 Extended Core SC140 Extended Core MQBus SC140 Extended Core 128 128 SQBus Boot ROM 64 Local Bus IP Master 32 Timers Memory
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MSC8122
16-Bit
SC140
RS-232
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PDF
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Untitled
Abstract: No abstract text available
Text: Freescale Semiconductor Technical Data MSC8122 Rev. 8, 7/2005 MSC8122 Quad Core 16-Bit Digital Signal Processor SC140 Extended Core SC140 Extended Core SC140 Extended Core MQBus SC140 Extended Core 128 128 SQBus Boot ROM 64 Local Bus IP Master 32 Timers Memory
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Original
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MSC8122
16-Bit
SC140
RS-232
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PDF
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Untitled
Abstract: No abstract text available
Text: Freescale Semiconductor Technical Data MSC8122 Rev. 9, 7/2005 MSC8122 Quad Core 16-Bit Digital Signal Processor SC140 Extended Core SC140 Extended Core SC140 Extended Core MQBus SC140 Extended Core 128 128 SQBus Boot ROM 64 Local Bus IP Master 32 Timers Memory
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Original
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MSC8122
16-Bit
SC140
RS-232
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PDF
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Untitled
Abstract: No abstract text available
Text: CY25561 Spread Spectrum Clock Generator Features By doing this, the measured EMI at the fundamental and harmonic frequencies of clock SSCLK is reduced. • 50 to 166 MHz operating frequency range ■ Wide range of spread selections: 9 This reduction in radiated energy can significantly reduce the
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CY25561
CY25561
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PDF
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PC133 registered reference design
Abstract: No abstract text available
Text: CDCVF2510 www.ti.com SCAS638C – JULY 2001 – REVISED APRIL 2006 3.3-V PHASE-LOCK LOOP CLOCK DRIVER FEATURES • • • • • • • • • • • • • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible
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CDCVF2510
SCAS638C
PC133
24-Pin
PC133 registered reference design
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PDF
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CDCVF2510
Abstract: CDCVF2510PW CDCVF2510PWR PC133 registered reference design
Text: CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS638B – DECEMBER 1999 – REVISED JULY 2001 D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible Operating Frequency 50 MHz to 175 MHz
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CDCVF2510
SCAS638B
PC133
PC133
24-Pin
CDCVF2510
CDCVF2510PW
CDCVF2510PWR
PC133 registered reference design
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PDF
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htc hd2 pinouts
Abstract: No abstract text available
Text: Freescale Semiconductor Technical Data Advance Information MSC8122 Rev. 4, 1/2005 MSC8122 Quad Core 16-Bit Digital Signal Processor SC140 Extended Core SC140 Extended Core SC140 Extended Core MQBus SC140 Extended Core 128 SQBus 128 Boot ROM 64 Local Bus IP Master
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MSC8122
MSC8122
16-Bit
htc hd2 pinouts
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PDF
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gt64460
Abstract: powerpc 7447a EN300386 tffs marvell ethernet switch sgmii sgmii marvell GR-1089 MPC7447A marvell discovery III Tornado 2.2
Text: Katana Qp • Single or Dual PowerPC™ MPC7447A processors running at up to 1.3GHz ■ 2-Way SMP Architecture ■ ATCA PICMG 3.1 Node 1000Base-T Base Fabric + Octal High Speed GbE Fabric ■ Layer 2 or 3 Ethernet switch option ■ Quad PTMC expansion sites
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MPC7447A
1000Base-T
128MB
TL-9000
platform500
GT64460
to166
256MB
gt64460
powerpc 7447a
EN300386
tffs
marvell ethernet switch sgmii
sgmii marvell
GR-1089
MPC7447A
marvell discovery III
Tornado 2.2
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PDF
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Untitled
Abstract: No abstract text available
Text: CDCVF2510 www.ti.com SCAS638C – JULY 2001 – REVISED APRIL 2006 3.3-V PHASE-LOCK LOOP CLOCK DRIVER FEATURES • • • • • • • • • • • • • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible
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CDCVF2510
SCAS638C
PC133
24-Pin
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PDF
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smd mark code zzz
Abstract: CY25701 CY25701FLXCT CY25701FLXIT CY3672 MARKING CODE SMD IC
Text: CY25701 Programmable High Frequency Crystal Oscillator with Spread Spectrum SSXO and No Spread Spectrum (XO) Option Features Benefits • Crystal Oscillator with Spread Spectrum Clock (SSXO) ■ Provides a wide range of spread percentages for maximum electromagnetic interference (EMI) reduction to meet
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CY25701
to166
smd mark code zzz
CY25701
CY25701FLXCT
CY25701FLXIT
CY3672
MARKING CODE SMD IC
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