Untitled
Abstract: No abstract text available
Text: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590 – DECEMBER 1997 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps Pulse Skew, tsk(p), Less Than 500 ps
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Original
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CDC319
10-LINE
SCAS590
1-to-10
MIL-STD-883,
28-Pin
scas590
CDC319DBR
CDC319IBIS
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442C – FEBRUARY 1994 – REVISED SEPTEMBER 2000 D D D D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC
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Original
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CDC2351
10-LINE
SCAS442C
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PDF
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CDC318
Abstract: No abstract text available
Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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Original
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CDC318
18-LINE
SCAS587B
1-to-18
MIL-STD-883,
48-Pin
CDC318
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PDF
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UT54AC
Abstract: No abstract text available
Text: Standard Products UT54ACTS899 RadHard 9-bit Latchable Transceiver with Parity Generator/Checker Datasheet March 14, 2007 www.aeroflex.com/radhard FEATURES PIN DESCRIPTION Latchable transceiver with output source/sink of 24mA Option to select generate parity and check or "feed-through"
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Original
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UT54ACTS899
28-pin
UT54AC
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PDF
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CDC319
Abstract: CDC319DB CDC319DBG4 CDC319DBR CDC319DBRG4 MO-150
Text: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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Original
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CDC319
10-LINE
SCAS590A
1-to-10
MIL-STD-883,
28-Pin
CDC319
CDC319DB
CDC319DBG4
CDC319DBR
CDC319DBRG4
MO-150
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PDF
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CDC319
Abstract: MO-150
Text: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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Original
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CDC319
10-LINE
SCAS590A
1-to-10
MIL-STD-883,
28-Pin
CDC319
MO-150
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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Original
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CDC318
18-LINE
SCAS587B
1-to-18
MIL-STD-883,
48-Pin
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PDF
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48-PIN
Abstract: CDC318A CDC318ADL CDC318ADLG4
Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications
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Original
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CDC318A
18-LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
CDC318A
CDC318ADL
CDC318ADLG4
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PDF
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48-PIN
Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR
Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications
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Original
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CDC318A
18LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
CDC318A
CDC318ADL
CDC318ADLG4
CDC318ADLR
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PDF
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CDC2351
Abstract: CDC2351DB CDC2351DBG4 CDC2351DBLE CDC2351DBR CDC2351DBRG4 CDC2351Q
Text: CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442D – FEBRUARY 1994 – REVISED SEPTEMBER 2000 D D D D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC
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Original
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CDC2351
10-LINE
SCAS442D
CDC2351
CDC2351DB
CDC2351DBG4
CDC2351DBLE
CDC2351DBR
CDC2351DBRG4
CDC2351Q
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PDF
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CDC351
Abstract: No abstract text available
Text: CDC351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995 D D D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC
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Original
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CDC351
10-LINE
SCAS441C
32-mA
CDC351
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PDF
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K3638
Abstract: 4Y04
Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications
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Original
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CDC318A
18-LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
K3638
4Y04
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC351. CDC351I 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS441D – FEBRUARY 1994 – REVISED OCTOBER 2003 FEATURES • DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
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Original
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CDC351.
CDC351I
10-LINE
SCAS441D
32-mA
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC2351ĆEP 1ĆLINE TO 10ĆLINE CLOCK DRIVER WITH 3ĆSTATE OUTPUTS SGLS248A − JUNE 2004 − REVISED AUGUST 2004 D Controlled Baseline D D D D D D D D D D Outputs Have Internal Series Damping − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of
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Original
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CDC2351EP
10LINE
SGLS248A
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PDF
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CDC2351
Abstract: CDC2351MDBREP MO-150
Text: CDC2351ĆEP 1ĆLINE TO 10ĆLINE CLOCK DRIVER WITH 3ĆSTATE OUTPUTS SGLS248A − JUNE 2004 − REVISED AUGUST 2004 D Controlled Baseline D D D D D D D D D D Outputs Have Internal Series Damping − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of
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Original
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CDC2351EP
10LINE
SGLS248A
CDC2351
CDC2351MDBREP
MO-150
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PDF
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Untitled
Abstract: No abstract text available
Text: PCK351 1:10 clock distribution device with 3-State outputs Rev. 01 — 14 May 2002 Product data 1. Description The PCK351 is a high-performance 3.3 V LVTTL clock distribution device. The PCK351 enables a single clock input to be distributed to ten outputs with minimum
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Original
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PCK351
PCK351
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC2351ĆEP 1ĆLINE TO 10ĆLINE CLOCK DRIVER WITH 3ĆSTATE OUTPUTS SGLS248A − JUNE 2004 − REVISED AUGUST 2004 D Controlled Baseline D D D D D D D D D D Outputs Have Internal Series Damping − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of
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Original
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CDC2351EP
10LINE
SGLS248A
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PDF
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CDC330
Abstract: No abstract text available
Text: CDC330 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS329A – OCTOBER 1993 – REVISED MARCH 1994 • • • • • • • • • DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs
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Original
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CDC330
SCAS329A
32-mA
CDC330
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PDF
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Untitled
Abstract: No abstract text available
Text: Standard Products UT54ACTS899 RadHard 9-bit Latchable Transceiver with Parity Generator/Checker Datasheet March, 2009 www.aeroflex.com/Logic FEATURES PIN DESCRIPTION Latchable transceiver with output source/sink of 24mA Option to select generate parity and check or "feed-through"
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Original
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UT54ACTS899
28-pin
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PDF
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CDC2351
Abstract: CDC2351DB CDC2351DBG4 CDC2351DBLE CDC2351DBR CDC2351DBRG4 CDC2351Q
Text: CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442D – FEBRUARY 1994 – REVISED SEPTEMBER 2000 D D D D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC
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Original
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CDC2351
10-LINE
SCAS442D
CDC2351
CDC2351DB
CDC2351DBG4
CDC2351DBLE
CDC2351DBR
CDC2351DBRG4
CDC2351Q
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PDF
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48-PIN
Abstract: CDC318A
Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications
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Original
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CDC318A
18LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
CDC318A
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PDF
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CDC2351PWRG4
Abstract: CDC2351 CDC2351DB CDC2351DBG4 CDC2351DBLE CDC2351DBR CDC2351DBRG4 CDC2351Q
Text: CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442D – FEBRUARY 1994 – REVISED SEPTEMBER 2000 D D D D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC
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Original
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CDC2351
10-LINE
SCAS442D
CDC2351PWRG4
CDC2351
CDC2351DB
CDC2351DBG4
CDC2351DBLE
CDC2351DBR
CDC2351DBRG4
CDC2351Q
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PDF
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MO-150
Abstract: CDC319
Text: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590 – DECEMBER 1997 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps Pulse Skew, tsk(p), Less Than 500 ps
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Original
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CDC319
10-LINE
SCAS590
1-to-10
MIL-STD-883,
28-Pin
MO-150
CDC319
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PDF
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54ALS161
Abstract: No abstract text available
Text: REVISIONS C Change VJL, tp clock , fflAX, and propagation delay limits. Delete minimum limits from IJL and propagation delays. Convert to military drawing format. Case E inactive for new design D Change drawing CAGE number to 67268. Change IJL condition. Change tpLH2 - Correct vendor p/n. Case 2, device types 01 and
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OCR Scan
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MIL-BUL-103.
MIL-BUL-103
54ALS161
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PDF
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