TRISTATE NAND Search Results

TRISTATE NAND Result Highlights (5)

Part	Manufacturer	Description
54LS126A/BCA	Rochester Electronics LLC	54LS126 - Quad bus buffer gates with Tristate Output - Dual marked (M38510/32302BCA)
DM74LS22J	Rochester Electronics LLC	DM74LS22 - NAND Logic Gate
54H30J/C	Rochester Electronics LLC	54H30 - NAND Gate
MC2101F	Rochester Electronics LLC	MC2101F - Dual NAND Logic Gate
54H30J	Rochester Electronics LLC	54H30 - NAND Gate

TRISTATE NAND Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
XC6200 Abstract: BUF C038 XC6264 xilinx XC6216 PN16 XC6209 XC6216 PW16 XC6000 N16O Text: XC6200 FPGA Family  Advanced Product Description Features • Flexible Pin Configuration - All User I/O’s programmable as in, out, bidirect, tristate or open drain. - Configurable pull-up/down resistors - CMOS or TTL logic levels - 8.32-bit CPU interface	Original	XC6200 32-bit 220MHz XC6216 -2PC84C -40oC -55oC 125oC 84-Pin TQ144 BUF C038 XC6264 xilinx XC6216 PN16 XC6209 PW16 XC6000 N16O	PDF
atmel 216 Abstract: ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state ATL35 atmel 334 20PCI atmel h 952 Text: Features • High-speed - 150 ps Gate Delay - 2-input NAND, FO = 2 nominal • Up to 2.7 Million Used Gates and 976 Pins • System Level Integration Technology – Cores: ARM7TDMI and AVR RISC Microcontrollers, OakDSP™ and LodeDSPCores™, 10T/100 Ethernet MAC, USB and PCI Cores	Original	10T/100 ATL35 0802E 10/99/0M atmel 216 ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state atmel 334 20PCI atmel h 952	PDF
TTL 1-of-8 encoder Abstract: 74LS 2-input OR gate 74LS series logic gates 3 input nand gate 74LS series logic gates 3 input or gate 74F374SC Text: 1/2 TTL LOGIC 74F SERIES 74F SERIES • 74F: EXCELLENT SPEED/POWER CONSUMPTION COMBINATION Part Number Description SQP £ ea. Gates & Inverters 74F00SC Quad 2-Input NAND Gate 74F02SC Quad 2-Input NOR Gate 74F04SC Hex Inverter 74F08SC Quad 2-Input AND Gate	Original	74F164ASC 74F194SC 74F299SC 74F350SC 74F378SC 74F379SC 74F398SC 74F399SC 74F675ASC 74F676SC TTL 1-of-8 encoder 74LS 2-input OR gate 74LS series logic gates 3 input nand gate 74LS series logic gates 3 input or gate 74F374SC	PDF
circuit diagram of Tri-State Buffer using CMOS Abstract: verilog code for UART with BIST capability block diagram for UART with BIST capability tri state AT28 vhdl code for flip-flop vhdl pid verilog code pid controller free vhdl code for usart Text: Features • 0.5 µm Drawn Gate Length 0.45 µm Leff Sea-of-Gates Architecture with • • • • • Triple-level Metal Embedded E2 Memory up to 256 Kb 3.3V Operation with 5.0V Tolerant Input and Output Buffers High-speed, 200 ps Gate Delay, 2-input NAND, FO = 2 Nominal	Original	10T/100 ATL50/E2 1173D 11/99/1M circuit diagram of Tri-State Buffer using CMOS verilog code for UART with BIST capability block diagram for UART with BIST capability tri state AT28 vhdl code for flip-flop vhdl pid verilog code pid controller free vhdl code for usart	PDF
Transistor Equivalent list po55 Abstract: Structure of D flip-flop DFFSR tristate buffer sis 968 PO-44Z PRU11 AC/DC drive nec 78054 PO22 tristate buffer cmos Text: Features • High Speed - 180 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.198 M Used Gates and 512 Pads with 3.3 V, 3V and 2.5V libraries when tested to space quality grades • Up to 1.6M Used Gates and 596 Pads with 3.3 V, 3V and 2.5V libraries when tested to	Original		PDF
74xxx Abstract: ic 74 LS 138 DECODER HC- 543 4046 analog IC tristate demultiplexer Schieberegister SR flip flop IC vhc 164 IC INVERTER 8-bit 4538 bcd Text: VHCT VHC LVXU LVCU LVCH X X X X X X X X X X X X X X STD X X X X X OL X LVX X X LVU X X LVT X LVQ X LVC X X X X X X X X X X X X X LV LCX X LS HCT HCU HC FCT F BCT ALS AL ACTQ ACT AC ABT xxx 74xxx Gatter AND OR NAND NOR Quad 2-Eingänge 08 Quad 2-Eingänge oc	Original	74xxx 13-Eing UK315358 74xxx ic 74 LS 138 DECODER HC- 543 4046 analog IC tristate demultiplexer Schieberegister SR flip flop IC vhc 164 IC INVERTER 8-bit 4538 bcd	PDF
tristate buffer Abstract: smd transistor AO HEX TO DECIMAL tristate buffer cmos A101 A201 MH1099E MH1156E PO11F MH1332E Text: Features • High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal • Up to 1.198M Used Gates and 512 Pads with 3.3V, 3V and 2.5V Libraries when Tested to Space Quality Grades • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries when Tested to	Original	4110F tristate buffer smd transistor AO HEX TO DECIMAL tristate buffer cmos A101 A201 MH1099E MH1156E PO11F MH1332E	PDF
PO88 Abstract: ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5 Text: Features • High Speed - 170 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.6 Million Used Gates and 596 pads, with 3.3V, 3V, and 2.5V libraries • System Level Integration Technology Cores on request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:	Original	250MHz 220MHz 800MHz 5962-01B01 PO88 ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5	PDF
AOI222 Abstract: AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter Text: Features • High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries • System Level Integration Technology Cores on Request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:	Original	5962-01B01 4138E AOI222 AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter	PDF
CB12000 Abstract: cd 4847 bt8c dc to ac inverter schematic CB22000 ld3p FD11S FD3S BUT12 BUT18 Text: CB22000 SERIES HCMOS STANDARD CELL GENERAL DESCRIPTION FEATURES 0.7 micron, double layer metal HCMOS4T process featuring self-aligned twin tub N and P wells, low resistance polysilicide gates and thin metal oxide. 2 - input NAND ND2P delay of 0.30 ns (typ)	Original	CB22000 CB12000 cd 4847 bt8c dc to ac inverter schematic ld3p FD11S FD3S BUT12 BUT18	PDF
AO4L Abstract: ld3p AO15A AO16A FD3S AO15AN AO23L BT8C datasheet MTC-35400 mux2*1 Text: MTC-35000 CMOS 0.5µ Standard Cell Library Services October ‘98 CMOS Family Features • Technology - 0.5µ CMOS for mixed analog 2 digital application - 0.5 micron CMOS transistors, triple layer metal, single or doble poly layer - Self-aligned twin tub Nand P-wells	Original	MTC-35000 102ps 216ps AO4L ld3p AO15A AO16A FD3S AO15AN AO23L BT8C datasheet MTC-35400 mux2*1	PDF
CD4043BCJ Abstract: CD4043BMJ CD4044BC DATA SHEET DOWNLOAD cd4043bcn C1995 CD4043B CD4043BC CD4043BM CD4044B CD4044BC Text: CD4043BM CD4043BC Quad TRI-STATE NOR R S Latches CD4044BM CD4044BC Quad TRI-STATE NAND R S Latches General Description Features CD4043BM CD4043BC are quad cross-couple TRI-STATE CMOS NOR latches and CD4044BM CD4044BC are quad cross-couple TRI-STATE CMOS NAND latches Each latch	Original	CD4043BM CD4043BC CD4044BM CD4044BC CD4043BCJ CD4043BMJ CD4044BC DATA SHEET DOWNLOAD cd4043bcn C1995 CD4043B CD4044B	PDF
DPRAM Abstract: 256K DPRAM ISB35083 ISB35130 ISB35166 ISB35208 ISB35279 ISB35389 ISB35484 ISB35666 Text: DIGITAL SEMICUSTOM CIRCUITS SEA OF GATES - STRUCTURED ARRAYS ISB 35000 SERIES 0.5 micron, triple level metal HCMOS Technology. Typical delay 0.21ns for 2-input NAND gate GENERAL FEATURES • ■ ■ ■ ■ ■ 0.5 micron triple layer metal HCMOS process featuring retrograde well technology, low resistance	Original		PDF
vhdl code for 4 bit carry look ahead adder Abstract: vhdl code for 8 bit carry look ahead adder DS3596-4 full adder circuit using nor gates vhdl code for carry look ahead adder DS3596 LAH3 vhdl code for 4 bit ripple COUNTER CERQUAD44 MA9600 Text: MA9000A Sea of MA9000A Gates Radiation hard Advance Gate Array Design System ReplacesJanuary 2000 version, DS3596-4.0 DS3596-4.1 July 2002 The logic building block is a cell-unit, equivalent in size to a two input NAND gate. Back-to-back cell units form the core of	Original	MA9000A MA9000A DS3596-4 vhdl code for 4 bit carry look ahead adder vhdl code for 8 bit carry look ahead adder full adder circuit using nor gates vhdl code for carry look ahead adder DS3596 LAH3 vhdl code for 4 bit ripple COUNTER CERQUAD44 MA9600	PDF

Untitled Abstract: No abstract text available Text: b O cl7M44 O O D S bb ? ÔS3 • MPS MP3274 m Fault Protected 32 Channel, 12-Bit Data Acquisition Subsystem M icro Power Systems FEATURES • Complete 32-Channel 12-Bit A/D Converter with Sample & Hold, Reference, Clock and TriState Outputs • Fast Conversion, less than 15p.S	OCR Scan	cl7M44 MP3274 12-Bit 32-Channel 12-Bit MP3274 32-ch	PDF
BCD 4543 Abstract: 4564 RAM 4 bit binary pipeline ripple carry adder 4558, 4560 74F701 Text: S* Section 4 Contents 54F/74F00 Quad 2-Input NAND G a te . 54F/74F02 Quad 2-Input NOR G a te .	OCR Scan	54F/74F00 54F/74F02 54F/74F04 54F/74F08 54F/74F10 54F/74F11 29F52 29F53 29F68 29F524 BCD 4543 4564 RAM 4 bit binary pipeline ripple carry adder 4558, 4560 74F701	PDF
74AC367 Abstract: 74ACT705 74ac2526 74ac2525 54AC/74AC2525 Text: Section 4 Contents 54AC/74AC00 Quad 2-Input NAND G a te . 54ACT/74ACT00 Quad 2-Input NAND Gate .	OCR Scan	54AC/74AC00 54ACT/74ACT00 54AC/74AC02 54ACT/74ACT02 54AC/74AC04 54ACT/74ACT04 AC2525 54AC/74AC2526 54AC/74AC2708 54ACT/74ACT2708 74AC367 74ACT705 74ac2526 74ac2525 54AC/74AC2525	PDF
TS 4142 Abstract: CT244 Text: Section 4 Contents 74VHC00, 74VHCT00 Quad 2-Input NAND G a te . 74VHC02 Quad 2-Input NOR G a te .	OCR Scan	74VHC00, 74VHCT00 74VHC02 74VHC04, 74VHCT04 74VHCU04 74VHC08, 74VHCT08 74VHC14 74VHC573, TS 4142 CT244	PDF
Untitled Abstract: No abstract text available Text: Section 8 LV X Family * Section 8 Contents LVX Family Features. 74LVX00 Low Voltage Quad 2-Input NAND G a t e .	OCR Scan	74LVX00 74LVX02 74LVX04 74LVX08 74LVX14 74LVX244 74LVX245 74LVX273 74LVX373 74LVX374	PDF
cd4044 Abstract: No abstract text available Text: February 1988 Semiconductor CD4043BM/CD4043BC Quad TRI-STATE NOR R /S Latches CD4044BM/CD4044BC Quad TRI-STATE NAND R /S Latches General Description Features CD4043BM/CD4043BC are quad cross-couple TRI-STATE CMOS NOR latches, and CD4044BM/CD4044BC are quad	OCR Scan	CD4043BM/CD4043BC CD4044BM/CD4044BC cd4044	PDF
LAH3 Abstract: No abstract text available Text: P jjp i G E C P L E S S E Y SE MI C ON DU CT ORS DS3596-2.4 MA9000A Sea of Gates RADIATION HARD ADVANCED GATE ARRAY DESIGN SYSTEM The logic building block is a cell-unit, equivalent ¡n size to a two input NAND gate. Back-to-back cell units form the core of	OCR Scan	DS3596-2 MA9000A 37bfl522 MA9000A 002H24T LAH3	PDF
cd40438m Abstract: CD40438CN CD40438 CD4043 CD40448 Text: CD4043BM/CD4043BC Quad TRI-STATE« NOR R/S Latches CD4044BM/CD4044BC Quad TRI-STATE NAND R/S Latches General Description Features CD4043BM/CD4043BC are quad cross-couple TRI-STATE CMOS NOR latches, and CD4044BM/CD4044BC are quad cross-couple TRI-STATE CMOS NANO latches. Each	OCR Scan	CD4043BM/CD4043BC CD4044BM/CD4044BC IBM/CD4G43BC, CD4044BM/CD4044BC CD4043BM/CD4043BC, cd40438m CD40438CN CD40438 CD4043 CD40448	PDF
MC14512 Abstract: CD4512C AN-90 CD4512M Text: CD4512M/CD45t yWA iMsnonai mm Semiconductor CD4512M/CD4512C 8-Channel Data Selector General Description Features The CD4512M/CD4512C 8-channel d a ta s e le c to r is a c om plem entary MOS CMOS c irc u it con structe d w ith Nand P-channel enhancem ent m ode tra n s is to rs . This data	OCR Scan	CD4512M/CD4512C MC14512 CD4512C AN-90 CD4512M	PDF
Untitled Abstract: No abstract text available Text: CD4043BM/CD4043BC Quad TRI-STATE0 NOR R/S Latches CD4044BM/CD4044BC Quad TRI-STATE NAND R/S Latches General Description Features CD4043BM/CD4043BC are quad cross-couple TRI-STATE CMOS NOR latches, and CD4044BM/CD4044BC are quad cross-couple TRI-STATE CMOS NAND latches. Each latch	OCR Scan	CD4043BM/CD4043BC/CD4044BM/CD4044BC CD4043BM/CD4043BC CD4044BM/CD4044BC CD4044BM/CD4044BC CD4043B CD4044B	PDF

TRISTATE NAND Search Results

TRISTATE NAND Result Highlights (5)

TRISTATE NAND Datasheets Context Search

XC6200

atmel 216

TTL 1-of-8 encoder

circuit diagram of Tri-State Buffer using CMOS

Transistor Equivalent list po55

74xxx

tristate buffer

PO88

AOI222

CB12000

AO4L

CD4043BCJ

DPRAM

vhdl code for 4 bit carry look ahead adder

Untitled

BCD 4543

74AC367

TS 4142

Untitled

cd4044

LAH3

cd40438m

MC14512

Untitled