pll_afi_clk
Abstract: No abstract text available
Text: Section IV. RLDRAM II Controller with UniPHY IP User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_RLDRAM_II_UG-2.0 Document Version: Document Date: 2.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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UniPHY
Abstract: DDR3 model verilog codes
Text: Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_QDRII_UG-2.0 Document Version: Document Date: 2.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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PCIe to Ethernet
Abstract: UniPHY RLDRAM DDR3 phy altera PCIe to Ethernet bridge DDR3 model verilog codes
Text: External Memory Interface Handbook Volume 3 Section IV. RLDRAM II Controller with UniPHY IP User Guide External Memory Interface Handbook Volume 3 Section IV. RLDRAM II Controller with UniPHY IP User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com
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DDR3 phy
Abstract: vhdl code for ddr3 ddr3 RDIMM pinout "DDR3 SDRAM" DDR3 DIMM 240 pinout DDR SDRAM Controller look-ahead policy sdram controller DDR3 slot 240 pinout UniPHY UniPHY ddr3 sdram
Text: Section V. DDR2 and DDR3 SDRAM Controller with UniPHY User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_DDR3UP_UG-1.0 Document Version: Document Date: 1.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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TSOT1610GA
Abstract: TSOT1610G D2488 1521-pin
Text: Product Description June 2004 MARS10G T-UniPHY TSOT1610GA SONET/SDH STS-192/STM-64 Overhead Terminator and Path Processor MARS10G T-UniPHY Overview The MARS10G T-UniPHY (TSOT1610GA) is a STS192/STM-64 overhead generator/terminator and path processor which can be used in many different
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MARS10G
TSOT1610GA)
STS-192/STM-64
STS192/STM-64
DS03-230SONT-8
TSOT1610GA
TSOT1610G
D2488
1521-pin
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UniPHY
Abstract: PCIe to Ethernet RTL 602 W
Text: External Memory Interface Handbook Volume 3 Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide External Memory Interface Handbook Volume 3 Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide 101 Innovation Drive San Jose, CA 95134
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Abstract: No abstract text available
Text: Initializing the UniPHY Nios II Sequencer in HardCopy Devices using FPP Configuration Scheme AN-650-1.0 Application Note This application note describes the reuse of the fast passive parallel FPP configuration interface, which is more commonly used in the Altera FPGA
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AN-650-1
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UniPHY
Abstract: EP4SE530H35C2 DDR3 pcb layout UniPHY ddr3 sdram PCB electronic components tutorials ddr3 ram micron ddr3 DDR3 embedded system SCHEMATIC MT49H16M36-18 MT41J64M16LA-15E IT
Text: Section II. UniPHY Design Tutorials 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_TUT_QDR-2.0 Document Version: Document Date: 2.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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Untitled
Abstract: No abstract text available
Text: External Memory Interfaces in Stratix V Devices 7 2012.12.28 SV51008 Subscribe Feedback The Stratix V devices provide an efficient architecture that allows you to fit wide external memory interfaces to support a high level of system bandwidth within the small modular I/O bank structure. The I/Os are
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SV51008
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Abstract: No abstract text available
Text: Cyclone V Device Datasheet February 2014 CV-51002-3.8 CV-51002-3.8 Datasheet This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Cyclone V devices. Cyclone V devices are offered in commercial and industrial grades. Commercial
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CV-51002-3
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PM4341
Abstract: PM4344 PM4351 PM6341 PM6344 PM7346 apc isdn 1207R
Text: PM7346 TM S/UNI- Preliminary Information QJET SATURN QUAD USER NETWORK INTERFACE FOR J2/E3/T3 FEATURES • Single chip quad ATM User Network Interface operating at 44.736 Mbit/s, 34.368 Mbit/s, and 6.312 Mbit/s conforming to ATMF95-1207R1, ATMF-94-0406R5, and
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PM7346
SPECTRA-155
PMC-970823
PM4341
PM4344
PM4351
PM6341
PM6344
PM7346
apc isdn
1207R
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lcsb
Abstract: PM5312 PM5344 PM5345
Text: PM5312 STTX Summary Information SONET/SDH TRANSPORT OVERHEAD TERMINATING TRANSCEIVER FEATURES • Monolithic SONET/SDH Transport Overhead Terminating Transceiver for use in STS-1, STS-3 STM-1 or STS12 (STM-4) applications. • Operates in STS-1 bit serial mode,
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PM5312
STS12
STS-12/
PM5345
S/UNI-155
PM5344
PM5312
PMC-931128
lcsb
PM5344
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LXT944
Abstract: PM3350 PM3351
Text: PM3351 Preliminary Information ELAN - TM 1x100 SINGLE PORT 10/100 Mbit/s ETHERNET SWITCH FEATURES • Single-chip, 1-port, full duplex or half duplex, 10/100BaseT switching device for low-cost unmanaged and managed networks. • Expansion port supports a peak
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PM3351
1x100
10/100BaseT
address3351
10BaseT
PM3350
10/100BaseT
PMC-970278
LXT944
PM3350
PM3351
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saf7730
Abstract: Philips SAF7730 TMS320DM310 saf77 full 18*16 barrel shifter design ADSP-215xx saf7730 audio TMS320DSC25 compare adsp 21xx with conventional processor compression pcm matlab
Text: EDN's 2003 DSP directory DSP shipments were tracking at 5% growth for 2002 until shipments in December ballooned. According to market-research company Forward Concepts www.forwardconcepts.com , this balloon in shipments netted an overall DSP-revenue growth of 14.1% for 2002. Wireless applications,
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1-800-477-8924-x4500
saf7730
Philips SAF7730
TMS320DM310
saf77
full 18*16 barrel shifter design
ADSP-215xx
saf7730 audio
TMS320DSC25
compare adsp 21xx with conventional processor
compression pcm matlab
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alt_iobuf
Abstract: ep3*SL150F1152C2 altera double data rate megafunction sdc UG-01032-4
Text: ALTDLL and ALTDQ_DQS Megafunctions User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 9.1 4.0 May 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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28HP
Abstract: pcie gen3 10GBASE-KR class 10 up board Datasheet 2012 CPRI Multi Rate datasheets of optical fpgas germanium power devices corporation germanium small signal power devices corporation pcie X1 edge connector pcie X8
Text: Introducing Innovations at 28 nm to Move Beyond Moore’s Law WP-01125-1.1 White Paper In addition to processing techniques, FPGA innovations allow Altera to move beyond Moore’s Law to meet higher bandwidth requirements while meeting cost and power budgets. Altera’s Stratix V FPGAs provide breakthrough bandwidth via 28-Gbps
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WP-01125-1
28-Gbps
ebcasts/all/wc-2010-introducing-stratix-v
28HP
pcie gen3
10GBASE-KR
class 10 up board Datasheet 2012
CPRI Multi Rate
datasheets of optical fpgas
germanium power devices corporation
germanium small signal power devices corporation
pcie X1 edge connector
pcie X8
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CKE 2009
Abstract: DDR2 sdram pcb layout guidelines EP4SE360 EP4SGX180 EP4SGX290 EP4SGX360 F572 QDR pcb layout DDR3 pcb layout guide DDR3 sdram pcb layout guidelines
Text: Section I. Device and Pin Planning 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_PLAN_PIN-2.0 Document Version: Document Date: 20 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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rty10
Abstract: PM5355 PM7322 RCMP-800
Text: PM7322 RCMP-800 Advance Information ATM L AYER C ELL R OUTING C ONTROL , MONITORING, • Two instantiations of policing per VC. • Low power, 0.6 micron, +5 Volt CMOS technology. PMC-941029 A4 • Outgoing OAM cells sourced from automatic OAM generating circuitry,
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PM7322
RCMP-800
PMC-941029
PM5347
PM7322
rty10
PM5355
RCMP-800
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AIIGX53001-3
Abstract: half bridge converter 2kw higig pause frame EP2AGX65 EP2AGX65DF29 HDTV transmitter receivers block diagram 32-Bit Parallel-IN Serial-OUT Shift Register prbs parity checker and generator SILICON General 741 PMD Motion
Text: Arria II GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-3.0 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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Msi 533 Motherboard
Abstract: MICRON ddr3 MT41J64M16 latest computer motherboard circuit diagram verilog code for pci express memory transaction MT41J64M16 JES79-3C UniPHY DDR3 "application note" Intel x58 MICRON ddr3 MT41J64M16 application
Text: PCI Express to External Memory Reference Design AN-431-1.4 Application Note Introduction The Altera PCI Express to External Memory Reference Design provides a sample interface between the Altera PCI Express MegaCore® function and a 64-bit external memory. Altera offers this reference design to demonstrate the operation of the PCI
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AN-431-1
64-bit
Msi 533 Motherboard
MICRON ddr3 MT41J64M16
latest computer motherboard circuit diagram
verilog code for pci express memory transaction
MT41J64M16
JES79-3C
UniPHY
DDR3 "application note"
Intel x58
MICRON ddr3 MT41J64M16 application
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tcam
Abstract: ternary content addressable memory 100GbE Altera Stratix V datasheets of optical fpgas 100g phy interlaken network processor receiver ber fec 100G 40GBASE-R 10Gbase-kr transmitter
Text: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs WP-01128-1.1 White Paper As various standard bodies finalize their 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want
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100-GbE
28-nm
WP-01128-1
40-GbE/100-GbE
tcam
ternary content addressable memory
100GbE
Altera Stratix V
datasheets of optical fpgas
100g phy
interlaken network processor
receiver ber fec 100G
40GBASE-R
10Gbase-kr transmitter
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lpddr2
Abstract: lpddr2 datasheet lpddr2 phy lpddr2 DQ calibration Datasheet LPDDR2 SDRAM DDR3L "Stratix IV" Package layout footprint HSUL-12 lpddr2 tutorial Verilog code of 1-bit full subtractor
Text: Stratix V Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V1-1.0 Copyright 2010Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words
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2010Altera
lpddr2
lpddr2 datasheet
lpddr2 phy
lpddr2 DQ calibration
Datasheet LPDDR2 SDRAM
DDR3L
"Stratix IV" Package layout footprint
HSUL-12
lpddr2 tutorial
Verilog code of 1-bit full subtractor
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ddr ram repair
Abstract: dc bfm Silicon Image 1364 Altera fft megacore design of dma controller using vhdl doorbell project Ethernet-MAC using vhdl ModelSim 6.5c pcie Gen2 payload verilog code for fir filter
Text: MegaCore IP Library Release Notes and Errata 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Library Version: 9.1 Document Version: 9.1.4 Document Date: 15 May 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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Untitled
Abstract: No abstract text available
Text: PM PM3350 PMC-Sierra, Inc. Preliminary Information E lan • E IG H T PO RT 10 M b it/s SW ITCH FEATURES Single-chip, 8-port 10BaseT Ethernet switch device for low-cost unmanaged and managed networks. On-chip SmartPath 50 MHz RISC CPU processor core, multi-channel
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PM3350
10BaseT
PM3351,
m100s.
10BaseT
10/100BaseT
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